
- •1. Description
- •2. Features
- •3. Block Diagram
- •4. SFR Mapping
- •5. Pin Configuration
- •6. TS80C52X2 Enhanced Features
- •6.1 X2 Feature
- •6.1.1 Description
- •6.2 Dual Data Pointer Register Ddptr
- •6.3 Timer 2
- •6.3.1 Auto-Reload Mode
- •6.3.2 Programmable Clock-Output
- •6.4 TS80C52X2 Serial I/O Port
- •6.4.1 Framing Error Detection
- •6.4.2 Automatic Address Recognition
- •6.4.3 Given Address
- •6.4.4 Broadcast Address
- •6.4.5 Reset Addresses
- •6.5 Interrupt System
- •6.6 Idle mode
- •6.7 Power-Down Mode
- •6.8 ONCETM Mode (ON Chip Emulation)
- •6.9 Power-Off Flag
- •6.10 Reduced EMI Mode
- •7.1 ROM Structure
- •7.2 ROM Lock System
- •7.2.1 Encryption Array
- •7.2.2 Program Lock Bits
- •7.2.3 Signature bytes
- •7.2.4 Verify Algorithm
- •8.1 EPROM Structure
- •8.2 EPROM Lock System
- •8.2.1 Encryption Array
- •8.2.2 Program Lock Bits
- •8.2.3 Signature bytes
- •8.3 EPROM Programming
- •8.3.1 Set-up modes
- •8.3.2 Definition of terms
- •8.3.3 Programming Algorithm
- •8.3.4 Verify algorithm
- •8.4 EPROM Erasure (Windowed Packages Only)
- •8.4.1 Erasure Characteristics
- •9. Signature Bytes
- •10. Electrical Characteristics
- •10.1 Absolute Maximum Ratings (1)
- •10.2 Power consumption measurement
- •10.3 DC Parameters for Standard Voltage
- •10.4 DC Parameters for Low Voltage
- •10.5 AC Parameters
- •10.5.1 Explanation of the AC Symbols
- •10.5.2 External Program Memory Characteristics
- •10.5.3 External Program Memory Read Cycle
- •10.5.4 External Data Memory Characteristics
- •10.5.5 External Data Memory Write Cycle
- •10.5.6 External Data Memory Read Cycle
- •10.5.7 Serial Port Timing - Shift Register Mode
- •10.5.8 Shift Register Timing Waveforms
- •10.5.9 EPROM Programming and Verification Characteristics
- •10.5.10 EPROM Programming and Verification Waveforms
- •10.5.11 External Clock Drive Characteristics (XTAL1)
- •10.5.12 External Clock Drive Waveforms
- •10.5.13 AC Testing Input/Output Waveforms
- •10.5.14 Float Waveforms
- •10.5.15 Clock Waveforms
- •11. Ordering Information

TS80C32X2
TS87C52X2
TS80C52X2
10.5.11 External Clock Drive Characteristics (XTAL1)
Table 36. AC Parameters
Symbol |
Parameter |
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Max |
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TCLCL |
Oscillator Period |
25 |
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TCHCX |
High Time |
5 |
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TCLCX |
Low Time |
5 |
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ns |
TCLCH |
Rise Time |
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ns |
TCHCL |
Fall Time |
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5 |
ns |
TCHCX/TCLCX |
Cyclic ratio in X2 mode |
40 |
60 |
% |
10.5.12 External Clock Drive Waveforms
VCC-0.5 V |
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0.7VCC |
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0.45 V |
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0.2VCC-0.1 V |
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TCHCL |
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CHCX |
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TCLCX |
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TCLCH |
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TCLCL |
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Figure 23. External Clock Drive Waveforms
10.5.13 AC Testing Input/Output Waveforms
VCC-0.5 V |
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0.2VCC+0.9 |
INPUT/OUTPUT |
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0.2VCC-0.1 |
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0.45 V |
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Figure 24. AC Testing Input/Output Waveforms
AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.
10.5.14 Float Waveforms
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FLOAT |
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VOH-0.1 V VLOAD |
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VLOAD+0.1 V |
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V +0.1 V |
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VLOAD-0.1 V |
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OL |
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Figure 25. Float Waveforms
Rev.D - 16 November, 2000 |
53 |

TS80C32X2
TS87C52X2
TS80C52X2
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20mA.
10.5.15 Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two.
INTERNAL |
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STATE4 |
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STATE5 |
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STATE6 |
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STATE1 |
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STATE2 |
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STATE3 |
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STATE4 |
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STATE5 |
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CLOCK |
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P1 |
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P2 |
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P1 |
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XTAL2 |
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EXTERNAL PROGRAM MEMORY FETCH |
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THESE SIGNALS ARE NOT ACTIVATED DURING THE |
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EXECUTION OF A MOVX INSTRUCTION |
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PSEN |
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P0 |
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DATA |
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PCL OUT |
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DATA |
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PCL OUT |
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DATA |
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PCL OUT |
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SAMPLED |
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SAMPLED |
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SAMPLED |
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FLOAT |
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FLOAT |
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FLOAT |
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P2 (EXT) |
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INDICATES ADDRESS TRANSITIONS |
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READ CYCLE |
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RD |
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PCL OUT (IF PROGRAM |
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MEMORY IS EXTERNAL) |
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P0 |
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DPL OR Rt OUT |
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P2 |
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FLOAT |
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INDICATES DPH OR P2 SFR TO PCH TRANSITION |
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WRITE CYCLE |
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PCL OUT (EVEN IF PROGRAM |
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MEMORY IS INTERNAL) |
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P0 |
DPL OR Rt OUT |
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DATA OUT |
PCL OUT (IF PROGRAM |
P2 |
INDICATES DPH OR P2 SFR TO PCH TRANSITION |
MEMORY IS EXTERNAL) |
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PORT OPERATION
OLD DATA |
NEW DATA |
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P0 PINS SAMPLED |
P0 PINS SAMPLED |
MOV DEST P0
MOV DEST PORT (P1, P2, P3) (INCLUDES INT0, INT1, TO, T1)
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
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P1, P2, P3 PINS SAMPLED |
P1, P2, P3 PINS SAMPLED |
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RXD SAMPLED |
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RXD SAMPLED |
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Figure 26. Clock Waveforms
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA=25° C fully loaded)
RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications.
54 |
Rev.D - 16 November, 2000 |