
- •1. Description
- •2. Features
- •3. Block Diagram
- •4. SFR Mapping
- •5. Pin Configuration
- •6. TS80C52X2 Enhanced Features
- •6.1 X2 Feature
- •6.1.1 Description
- •6.2 Dual Data Pointer Register Ddptr
- •6.3 Timer 2
- •6.3.1 Auto-Reload Mode
- •6.3.2 Programmable Clock-Output
- •6.4 TS80C52X2 Serial I/O Port
- •6.4.1 Framing Error Detection
- •6.4.2 Automatic Address Recognition
- •6.4.3 Given Address
- •6.4.4 Broadcast Address
- •6.4.5 Reset Addresses
- •6.5 Interrupt System
- •6.6 Idle mode
- •6.7 Power-Down Mode
- •6.8 ONCETM Mode (ON Chip Emulation)
- •6.9 Power-Off Flag
- •6.10 Reduced EMI Mode
- •7.1 ROM Structure
- •7.2 ROM Lock System
- •7.2.1 Encryption Array
- •7.2.2 Program Lock Bits
- •7.2.3 Signature bytes
- •7.2.4 Verify Algorithm
- •8.1 EPROM Structure
- •8.2 EPROM Lock System
- •8.2.1 Encryption Array
- •8.2.2 Program Lock Bits
- •8.2.3 Signature bytes
- •8.3 EPROM Programming
- •8.3.1 Set-up modes
- •8.3.2 Definition of terms
- •8.3.3 Programming Algorithm
- •8.3.4 Verify algorithm
- •8.4 EPROM Erasure (Windowed Packages Only)
- •8.4.1 Erasure Characteristics
- •9. Signature Bytes
- •10. Electrical Characteristics
- •10.1 Absolute Maximum Ratings (1)
- •10.2 Power consumption measurement
- •10.3 DC Parameters for Standard Voltage
- •10.4 DC Parameters for Low Voltage
- •10.5 AC Parameters
- •10.5.1 Explanation of the AC Symbols
- •10.5.2 External Program Memory Characteristics
- •10.5.3 External Program Memory Read Cycle
- •10.5.4 External Data Memory Characteristics
- •10.5.5 External Data Memory Write Cycle
- •10.5.6 External Data Memory Read Cycle
- •10.5.7 Serial Port Timing - Shift Register Mode
- •10.5.8 Shift Register Timing Waveforms
- •10.5.9 EPROM Programming and Verification Characteristics
- •10.5.10 EPROM Programming and Verification Waveforms
- •10.5.11 External Clock Drive Characteristics (XTAL1)
- •10.5.12 External Clock Drive Waveforms
- •10.5.13 AC Testing Input/Output Waveforms
- •10.5.14 Float Waveforms
- •10.5.15 Clock Waveforms
- •11. Ordering Information

TS80C32X2
TS87C52X2
TS80C52X2
8. TS87C52X2
8.1 EPROM Structure
The TS87C52X2 is divided in two different arrays:
●the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Kbytes.
●the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes. In addition a third non programmable array is implemented:
●the signature array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes.
8.2 EPROM Lock System
The program Lock system, when programmed, protects the on-chip program against software piracy.
8.2.1 Encryption Array
Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. For this reason all the unused code bytes should be programmed with random values. This will ensure program protection.
8.2.2 Program Lock Bits
The three lock bits, when programmed according to Table 19., will provide different level of protection for the on-chip code and data.
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Table 19. Program Lock bits |
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Program Lock Bits |
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Protection description |
Security |
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LB1 |
LB2 |
LB3 |
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level |
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No program lock features enabled. Code verify will still be encrypted by the encryption |
1 |
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U |
U |
U |
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array if programmed. MOVC instruction executed from external program memory |
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returns non encrypted data. |
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MOVC instruction executed from external program memory are disabled from fetching |
2 |
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P |
U |
U |
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code bytes from internal memory, EA is sampled and latched on reset, and further |
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programming of the EPROM is disabled. |
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3 |
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U |
P |
U |
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Same as 2, also verify is disabled. |
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4 |
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U |
U |
P |
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Same as 3, also external execution is disabled. |
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U: unprogrammed,
P: programmed
WARNING: Security level 2 and 3 should only be programmed after EPROM and Core verification.
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Rev.D - 16 November, 2000 |