
- •Features
- •Pin Configuration
- •Description
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE2..PE0)
- •RESET
- •XTAL1
- •XTAL2
- •Crystal Oscillator
- •EEPROM Data Memory
- •SRAM Data Memory
- •I/O Direct
- •Data Direct
- •Data Indirect with Displacement
- •Data Indirect
- •l/O Memory
- •Status Register – SREG
- •Stack Pointer – SP
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Interrupt Handling
- •Interrupt Response Time
- •External Interrupts
- •Sleep Modes
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Timer/Counters
- •Timer Counter0 – TCNT0
- •Timer/Counter2 – TCNT2
- •Timer/Counter1
- •Timer/Counter1 in PWM Mode
- •Watchdog Timer
- •SS Pin Functionality
- •Data Modes
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •UARTs
- •Data Transmission
- •Data Reception
- •UART Control
- •Baud Rate Generator
- •Analog Comparator
- •Interface to External Memory
- •I/O Ports
- •Port A
- •Port A Data Register – PORTA
- •Port A as General Digital I/O
- •Port A Schematics
- •Port B
- •Port B Data Register – PORTB
- •Port B as General Digital I/O
- •Port B Schematics
- •Port C
- •Port C Data Register – PORTC
- •Port C as General Digital I/O
- •Port C Schematics
- •Port D
- •Port D Data Register – PORTD
- •Port D as General Digital I/O
- •Alternate Functions of Port D
- •Port D Schematics
- •Port E
- •Port E Data Register – PORTE
- •Port E as General Digital I/O
- •Alternate Functions of Port E
- •Port E Schematics
- •Boot Loader Support
- •Setting the Boot Loader Lock Bits by SPM
- •Performing Page Erase by SPM
- •Fill the Temporary Buffer
- •Perform a Page Write
- •Reading the Fuse and Lock Bits from Software
- •Fuse Bits
- •Signature Bytes
- •Parallel Programming
- •Signal Names
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Fuse Bits
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Data Memory Timing
- •Ordering Information
- •Packaging Information

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ATmega161(L) |
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Pin Descriptions |
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VCC |
Supply voltage. |
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GND |
Ground. |
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Port A (PA7..PA0) |
Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors |
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(selected for each bit). The Port A output buffers can sink 20 mA and can drive LED dis- |
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plays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low, |
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they will source current if the internal pull-up resistors are activated. The Port A pins are |
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tri-stated when a reset condition becomes active, even if the clock is not running. |
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Port A serves as a Multiplexed Address/Data port when using external memory |
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interface. |
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Port B (PB7..PB0) |
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output |
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buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source |
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current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset |
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condition becomes active, even if the clock is not running. |
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Port B also serves the functions of various special features of the ATmega161 as listed |
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on page 90. |
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Port C (PC7..PC0) |
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port C output |
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buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source |
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current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset |
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condition becomes active, even if the clock is not running. |
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Port C also serves as an address high output when using external memory interface. |
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Port D (PD7..PD0) |
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output |
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buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source |
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current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset |
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condition becomes active, even if the clock is not running. |
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Port D also serves the functions of various special features of the ATmega161 as listed |
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on page 99. |
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Port E (PE2..PE0) |
Port E is a 3-bit bi-directional I/O port with internal pull-up resistors. The Port E output |
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buffers can sink 20 mA. As inputs, Port E pins that are externally pulled low will source |
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current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset |
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condition becomes active, even if the clock is not running. |
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Port E also serves the functions of various special features of the ATmega161 as listed |
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on page 105. |
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Reset input. A low level on this pin for more than 500 ns will generate a reset, even if the |
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RESET |
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clock is not running. Shorter pulses are not guaranteed to generate a reset. |
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XTAL1 |
Input to the inverting oscillator amplifier and input to the internal clock operating circuit. |
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XTAL2 |
Output from the inverting oscillator amplifier. |
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1228B–09/01