- •Features
- •Pin Configuration
- •Description
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE2..PE0)
- •RESET
- •XTAL1
- •XTAL2
- •Crystal Oscillator
- •EEPROM Data Memory
- •SRAM Data Memory
- •I/O Direct
- •Data Direct
- •Data Indirect with Displacement
- •Data Indirect
- •l/O Memory
- •Status Register – SREG
- •Stack Pointer – SP
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Interrupt Handling
- •Interrupt Response Time
- •External Interrupts
- •Sleep Modes
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Timer/Counters
- •Timer Counter0 – TCNT0
- •Timer/Counter2 – TCNT2
- •Timer/Counter1
- •Timer/Counter1 in PWM Mode
- •Watchdog Timer
- •SS Pin Functionality
- •Data Modes
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •UARTs
- •Data Transmission
- •Data Reception
- •UART Control
- •Baud Rate Generator
- •Analog Comparator
- •Interface to External Memory
- •I/O Ports
- •Port A
- •Port A Data Register – PORTA
- •Port A as General Digital I/O
- •Port A Schematics
- •Port B
- •Port B Data Register – PORTB
- •Port B as General Digital I/O
- •Port B Schematics
- •Port C
- •Port C Data Register – PORTC
- •Port C as General Digital I/O
- •Port C Schematics
- •Port D
- •Port D Data Register – PORTD
- •Port D as General Digital I/O
- •Alternate Functions of Port D
- •Port D Schematics
- •Port E
- •Port E Data Register – PORTE
- •Port E as General Digital I/O
- •Alternate Functions of Port E
- •Port E Schematics
- •Boot Loader Support
- •Setting the Boot Loader Lock Bits by SPM
- •Performing Page Erase by SPM
- •Fill the Temporary Buffer
- •Perform a Page Write
- •Reading the Fuse and Lock Bits from Software
- •Fuse Bits
- •Signature Bytes
- •Parallel Programming
- •Signal Names
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Fuse Bits
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Data Memory Timing
- •Ordering Information
- •Packaging Information
ATmega161(L)
Description
The ATmega161 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega161 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code-efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega161 provides the following features: 16K bytes of In-System or Selfprogrammable Flash, 512 bytes EEPROM, 1K byte of SRAM, 35 general-purpose I/O lines, 32 general purpose working registers, Real-time Counter, 3 flexible timer/counters with compare modes, internal and external interrupts, 2 programmable serial UARTs, programmable Watchdog Timer with internal oscillator, an SPI serial port and 3 soft- ware-selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The Power-down mode saves the register and SRAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. In Power-save mode, the timer oscillator continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip Flash program memory can be reprogrammed using the self-programming capability through the boot block and an ISP through the SPI port, or by using a conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel ATmega161 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications.
The ATmega161 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators and evaluation kits.
3
1228B–09/01
Block Diagram
Figure 1. The ATmega161 Block Diagram
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PA0-PA7 |
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PC0-PC7 |
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VCC |
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PORTA DRIVERS |
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PORTC DRIVERS |
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GND |
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DATA REGISTER |
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DATA DIR. |
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DATA REGISTER |
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DATA DIR. |
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PORTA |
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REG. PORTA |
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PORTC |
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REG. PORTC |
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8-BIT DATA BUS |
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XTAL1 |
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INTERNAL |
OSCILLATOR |
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OSCILLATOR |
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PROGRAM |
STACK |
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WATCHDOG |
TIMING AND |
XTAL2 |
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RESET |
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COUNTER |
POINTER |
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TIMER |
CONTROL |
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PROGRAM |
SRAM |
MCU CONTROL |
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FLASH |
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REGISTER |
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INSTRUCTION |
GENERAL |
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TIMER/ |
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REGISTER |
PURPOSE |
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COUNTERS |
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REGISTERS |
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INSTRUCTION |
X |
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INTERRUPT |
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Y |
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DECODER |
Z |
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UNIT |
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CONTROL |
ALU |
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EEPROM |
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LINES |
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STATUS |
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REGISTER |
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PROGRAMMING |
SPI |
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UARTS |
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LOGIC |
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ANALOG COMPARATOR |
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DATA REG. |
REG. PORTE |
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DATA REGISTER |
DATA DIR. |
DATA REGISTER |
DATA DIR. |
PORTE |
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PORTB |
REG. PORTB |
PORTD |
REG. PORTD |
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- + |
PORTB DRIVERS |
PORTD DRIVERS |
PORTE DRIVERS |
PB0 - PB7 |
PD0 - PD7 |
PE0 - PE2 |
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4 ATmega161(L)
1228B–09/01
