UARTs
Data Transmission
The ATmega161 features two full-duplex (separate receive and transmit registers) Universal Asynchronous Receiver and Transmitters (UARTs). The main features are:
•Baud Rate Generator Generates any Baud Rate
•High Baud Rates at low XTAL Frequencies
•8 or 9 Bits Data
•Noise Filtering
•Overrun Detection
•Framing Error Detection
•False Start Bit Detection
•Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete
•Multi-processor Communication Mode
•Double-speed UART Mode
A block schematic of the UART transmitter is shown in Figure 45. The two UARTs are identical and the functionality is described in general for the two UARTs.
Figure 45. |
UART Transmitter |
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
DATA BUS |
|
|
|
|
|
|
|
||
XTAL |
BAUD RATE |
BAUD x 16 |
/16 |
|
|
|
|
UART I/O DATA |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
GENERATOR |
|
|
|
|
REGISTER (UDRn) |
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
STORE UDRn |
|
|
|
|
|
|
|
|
|
|
|
|
|
SHIFT ENABLE |
|
|
|
|
|
|
|
|
PIN CONTROL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
LOGIC |
|
CONTROL LOGIC |
|
BAUD |
|
|
|
10(11)-BIT TX |
|
|
TXDn |
PD1/ |
|||
|
|
|
|
|
SHIFT REGISTER |
|
|
|
PB3 |
||||
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
IDLE |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RXENn |
TXENn |
CHR9n |
RXB8n |
TXB8n |
RXCn TXCn UDREn FEn |
ORn |
U2Xn |
MPCMPn |
|
|
UART CONTROL AND |
UART CONTROL AND |
|||||||||||
|
STATUS REGISTER |
STATUS REGISTER |
|||||||||||
|
|
|
|
(UCSRnB) |
|
(UCSRnA) |
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RXCIEn |
|
TXCIEn |
UDRIEn |
|
|
DATA BUS |
|
TXCn UDREn |
|
|
||
|
|
||||||||||||
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TXCn |
UDREn |
n = 0,1 |
IRQ |
IRQ |
Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Register, UDRn. Data is transferred from UDRn to the Transmit shift register when:
•A new character has been written to UDRn after the stop bit from the previous character has been shifted out. The shift register is loaded immediately.
68 ATmega161(L)
1228B–09/01
ATmega161(L)
•A new character has been written to UDRn before the stop bit from the previous character has been shifted out. The shift register is loaded when the stop bit of the character currently being transmitted has been shifted out.
If the 10(11)-bit Transmit shift register is empty, data is transferred from UDRn to the shift register. At this time the UDREn (UART Data Register Empty) bit in the UART Control and Status Register, UCSRnA, is set. When this bit is set (one), the UART is ready to receive the next character. At the same time as the data is transferred from UDRn to the 10(11)-bit shift register, bit 0 of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9-bit data word is selected (the CHR9n bit in the UART Control and Status Register, UCSRnB, is set), the TXB8 bit in UCSRnB is transferred to bit 9 in the Transmit shift register.
On the baud rate clock following the transfer operation to the shift register, the start bit is shifted out on the TXDn pin. Then follows the data, LSB first. When the stop bit has been shifted out, the shift register is loaded if any new data has been written to the UDRn during the transmission. During loading, UDREn is set. If there is no new data in the UDRn register to send when the stop bit is shifted out, the UDREn flag will remain set until UDRn is written again. When no new data has been written and the stop bit has been present on TXDn for one bit length, the TX Complete flag (TXCn) in UCSRnA is set.
The TXENn bit in UCSRnB enables the UART transmitter when set (one). When this bit is cleared (zero), the PD1 (UART0) or PB3 (UART1) pin can be used for general I/O. When TXENn is set, the UART transmitter will be connected to PD1 (UART0) or PB3 (UART1), which is forced to be an output pin regardless of the setting of the DDD1 bit in DDRD (UART0) or DDB3 in DDRB (UART1). Note that PB3 (UART1) also is used as one of the input pins to the Analog Comparator. It is therefore not recommended to use UART1 if the Analog Comparator is also used in the application at the same time.
69
1228B–09/01