External Interrupts
MCU Control Register –
MCUCR
• Bit 3 – ICF1: Input Capture Flag 1
The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register (ICR1). ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.
• Bit 2 – OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 (Output Compare Register 2). OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE2 (Timer/Counter2 Compare match InterruptA Enable) and the OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed.
• Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0 (Timer/Counter0 Overflow Interrupt Enable) and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.
• Bit 2 – OCF0: Output Compare Flag 0
The OCF0 bit is set (one) when compare match occurs between the Timer/Counter0 and the data in OCR0 (Output Compare Register 0). OCF0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE0 (Timer/Counter0 Compare match InterruptA Enable) and the OCF0 are set (one), the Timer/Counter0 Compare match Interrupt is executed.
The external interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts will trigger even if the INT0/INT1/INT2 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level (INT2 is only an edge triggered interrupt). This is set up as indicated in the specification for the MCU Control Register – MCUCR (INT0/INT1) and EMCUCR (INT2). When the external interrupt is enabled and is configured as level triggered (only INT0/INT1), the interrupt will trigger as long as the pin is held low.
The MCU Control Register contains control bits for general MCU functions.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
$35 ($55) |
SRE |
SRW10 |
SE |
SM1 |
ISC11 |
ISC10 |
ISC01 |
ISC00 |
MCUCR |
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
• Bit 7 – SRE: External SRAM Enable
When the SRE bit is set (one), the external data memory interface is enabled and the pin functions AD0 - 7 (Port A), A8 - 5 (Port C), ALE (Port E), WR, and RD (Port D) are activated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction registers. See Figure 51 through Figure 54 for a description of the external memory pin functions. When the SRE bit is cleared (zero), the
34 ATmega161(L)
1228B–09/01
ATmega161(L)
external data memory interface is disabled and the normal pin and data direction settings are used.
• Bit 6 – SRW10: External SRAM Wait State
The SRW10 bit is used to set up extra wait states in the external memory interface. See “Double-speed Transmission” on page 77 for a detailed description.
• Bit 5 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before the execution of the SLEEP instruction.
• Bit 4 – SM1: Sleep Mode Select Bit 1
The SM1 bit, together with the SM0 control bit in EMCUCR, selects between the three available sleep modes as shown in Table 6.
Table 6. Sleep Mode Select
SM1 |
SM0 |
Sleep Mode |
|
|
|
0 |
0 |
Idle |
|
|
|
0 |
1 |
Reserved |
|
|
|
1 |
0 |
Power-down |
|
|
|
1 |
1 |
Power-save |
|
|
|
• Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask in the GIMSK are set. The level and edges on the external INT1 pin that activate the interrupt are defined in Table 7. The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.
Table 7. Interrupt 1 Sense Control
ISC11 |
ISC10 |
Description |
|
|
|
0 |
0 |
The low level of INT1 generates an interrupt request. |
|
|
|
0 |
1 |
Any logical change on INT1 generates an interrupt request. |
|
|
|
1 |
0 |
The falling edge of INT1 generates an interrupt request. |
|
|
|
1 |
1 |
The rising edge of INT1 generates an interrupt request. |
|
|
|
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask is set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 8. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.
35
1228B–09/01
Table 8. Interrupt 0 Sense Control
ISC01 |
ISC00 |
Description |
|
|
|
0 |
0 |
The low level of INT0 generates an interrupt request. |
|
|
|
0 |
1 |
Any logical change on INT0 generates an interrupt request. |
|
|
|
1 |
0 |
The falling edge of INT0 generates an interrupt request. |
|
|
|
1 |
1 |
The rising edge of INT0 generates an interrupt request. |
|
|
|
Extended MCU Control |
The Extended MCU Control Register contains control bits for external interrupt 2, sleep |
|||||||||
Register – EMCUCR |
mode bit and control bits for the external memory interface. |
|
|
|
||||||
|
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
$36 ($56) |
SM0 |
SRL2 |
SRL1 |
SRL0 |
SRW01 |
SRW00 |
SRW11 |
ISC2 |
EMCUCR |
|
|
|
|
|
|
|
|
|
|
|
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
• Bit 7 – SM0: Sleep Mode Bit 0
When this bit is set (one) and sleep mode bit 1 (SM1) in MCUCR is set, Power-save mode is selected as sleep mode. Refer to page 37 for a detailed description of the sleep modes.
• Bits 6..4 – SRL2, SRL1, SRL0: External SRAM Limit
It is possible to configure different wait states for different external memory addresses in ATmega161. The SRL2 - SRL0 bits are used to define at which address the different wait states will be configured. See “Interface to External Memory” on page 82 for a detailed description.
• Bits 3..1 – SRW01, SRW00, SRW11: External SRAM Wait State Select Bits
The SRW01, SRW00 and SRW11 bits are used to set up extra wait states in the external memory interface. See “Interface to External Memory” on page 82 for a detailed description.
• Bit 0 – ISC2: Interrupt Sense Control 2
The external interrupt 2 is activated by the external pin INT2 if the SREG I-flag and the corresponding interrupt mask in the GIMSK are set. If ISC2 is cleared (zero), a falling edge on INT2 activates the interrupt. If ISC2 is set (one), a rising edge on INT2 activates the interrupt. Edges on INT2 are registered asynchronously. Pulses on INT2 wider than 50 ns will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
When changing the ISC2 bit, an interrupt can occur. Therefore, it is recommended to first disable INT2 by clearing its Interrupt Enable bit in the GIMSK register. Then, ISC2 bit can be changed. Finally, the INT2 interrupt flag should be cleared by writing a logical “1” to its Interrupt Flag bit in the GIFR register before the interrupt is re-enabled.
36 ATmega161(L)
1228B–09/01