
- •Features
- •Pin Configuration
- •Description
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE2..PE0)
- •RESET
- •XTAL1
- •XTAL2
- •Crystal Oscillator
- •EEPROM Data Memory
- •SRAM Data Memory
- •I/O Direct
- •Data Direct
- •Data Indirect with Displacement
- •Data Indirect
- •l/O Memory
- •Status Register – SREG
- •Stack Pointer – SP
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Interrupt Handling
- •Interrupt Response Time
- •External Interrupts
- •Sleep Modes
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Timer/Counters
- •Timer Counter0 – TCNT0
- •Timer/Counter2 – TCNT2
- •Timer/Counter1
- •Timer/Counter1 in PWM Mode
- •Watchdog Timer
- •SS Pin Functionality
- •Data Modes
- •SPI Control Register – SPCR
- •SPI Status Register – SPSR
- •SPI Data Register – SPDR
- •UARTs
- •Data Transmission
- •Data Reception
- •UART Control
- •Baud Rate Generator
- •Analog Comparator
- •Interface to External Memory
- •I/O Ports
- •Port A
- •Port A Data Register – PORTA
- •Port A as General Digital I/O
- •Port A Schematics
- •Port B
- •Port B Data Register – PORTB
- •Port B as General Digital I/O
- •Port B Schematics
- •Port C
- •Port C Data Register – PORTC
- •Port C as General Digital I/O
- •Port C Schematics
- •Port D
- •Port D Data Register – PORTD
- •Port D as General Digital I/O
- •Alternate Functions of Port D
- •Port D Schematics
- •Port E
- •Port E Data Register – PORTE
- •Port E as General Digital I/O
- •Alternate Functions of Port E
- •Port E Schematics
- •Boot Loader Support
- •Setting the Boot Loader Lock Bits by SPM
- •Performing Page Erase by SPM
- •Fill the Temporary Buffer
- •Perform a Page Write
- •Reading the Fuse and Lock Bits from Software
- •Fuse Bits
- •Signature Bytes
- •Parallel Programming
- •Signal Names
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Fuse Bits
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Data Memory Timing
- •Ordering Information
- •Packaging Information

Features
•High-performance, Low-power AVR® 8-bit Microcontroller
•Advanced RISC Architecture
–130 Powerful Instructions – Most Single Clock Cycle Execution
–32 x 8 General Purpose Working Registers
–Fully Static Operation
–Up to 8 MIPS Throughput at 8 MHz
–On-chip 2-cycle Multiplier
•Program and Data Memories
–16K Bytes of Nonvolatile In-System Programmable Flash Endurance: 1,000 Write/Erase Cycles
–Optional Boot Code Memory with Independent Lock Bits Self-programming of Program and Data Memories
–512 Bytes of Nonvolatile In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles
–1K Byte of Internal SRAM
–Programming Lock for Software Security
•Peripheral Features
–Two 8-bit Timer/Counters with Separate Prescaler and PWM
–Expanded 16-bit Timer/Counter System with Separate Prescaler, Compare, Capture Modes and Dual 8-, 9-, or 10-bit PWM
–Dual Programmable Serial UARTs
–Master/Slave SPI Serial Interface
–Real-time Counter with Separate Oscillator
–Programmable Watchdog Timer with Separate On-chip Oscillator
–On-chip Analog Comparator
•Special Microcontroller Features
–Power-on Reset and Programmable Brown-out Detection
–External and Internal Interrupt Sources
–Three Sleep Modes: Idle, Power-save and Power-down
•Power Comsumption at 4 MHz, 3.0V, 25°C
–Active 3.0 mA
–Idle Mode 1.2 mA
–Power-down Mode < 1 µA
•I/O and Packages
–35 Programmable I/O Lines
–40-lead PDIP and 44-lead TQFP
•Operating Voltages
–2.7V - 5.5V for the ATmega161L
–4.0V - 5.5V for the ATmega161
•Speed Grades
–0 - 4 MHz for the ATmega161L
–0 - 8 MHz for the ATmega161
•Commercial and Industrial Temperature Ranges
8-bit Microcontroller with 16K Bytes of In-System Programmable Flash
ATmega161
ATmega161L
Rev. 1228B–09/01
1

Pin Configuration
PDIP
(OC0/T0) PB0 |
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1 |
40 |
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VCC |
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(OC2/T1) PB1 |
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2 |
39 |
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PA0 (AD0) |
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(RXD1/AIN0) PB2 |
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3 |
38 |
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PA1 (AD1) |
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(TXD1/AIN1) PB3 |
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4 |
37 |
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PA2 (AD2) |
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(SS) PB4 |
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5 |
36 |
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PA3 (AD3) |
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(MOSI) PB5 |
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6 |
35 |
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PA4 (AD4) |
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(MISO) PB6 |
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7 |
34 |
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PA5 (AD5) |
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(SCK) PB7 |
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8 |
33 |
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PA6 (AD6) |
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9 |
32 |
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RESET |
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PA7 (AD7) |
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(RXD0) PD0 |
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10 |
31 |
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PE0 (ICP/INT2) |
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(TXD0) PD1 |
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11 |
30 |
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PE1 (ALE) |
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(INT0) PD2 |
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12 |
29 |
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PE2 (OC1B) |
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(INT1) PD3 |
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13 |
28 |
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PC7 (A15) |
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(TOSC1) PD4 |
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14 |
27 |
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PC6 (A14) |
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(OC1A/TOSC2) PD5 |
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15 |
26 |
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PC5 (A13) |
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16 |
25 |
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PC4 (A12) |
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(WR) |
PD6 |
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PD7 |
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17 |
24 |
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PC3 (A11) |
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(RD) |
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XTAL2 |
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18 |
23 |
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PC2 (A10) |
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XTAL1 |
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19 |
22 |
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PC1 (A9) |
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GND |
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20 |
21 |
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PC0 (A8) |
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TQFP
PB4 (SS) |
PB3 (TXD1/AIN1) |
PB2 (RXD1/AIN0) |
PB1 (OC2/T1) |
PB0 (OC0/T0) |
NC* |
VCC |
PA0 (AD0) |
PA1 (AD1) |
PA2 (AD2) |
PA3 (AD3) |
44 |
43 |
42 |
41 |
40 |
39 |
38 |
37 |
36 |
35 |
34 |
(MOSI) PB5 1 (MISO) PB6
2 (SCK) PB7
3
RESET 4 (RXD0) PD0
5 NC*
6 (TXD0) PD1
7 (INT0) PD2
8 (INT1) PD3
9
(TOSC1) PD4 10 (OCIA/TOSC2) PD5
11
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
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(WR) PD6 |
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(RD) PD7 |
XTAL2 |
XTAL1 |
GND |
NC* |
(A8) PC0 |
(A9) PC1 |
(A10) PC2 |
(A11) PC3 |
(A12) PC4 |
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33 PA4 (AD4)
32 PA5 (AD5)
31 PA6 (AD6)
30 PA7 (AD7)
29 PE0 (ICP/INT2)
28 NC*
27 PE1 (ALE)
26 PE2 (OC1B)
25 PC7 (A15)
24 PC6 (A14)
23 PC5 (A13)
* NC = Do not connect
(Can be used in future devices)
2 ATmega161(L)
1228B–09/01