ATtiny26(L)
System Clock and
Clock Options
Clock Systems and their Distribution
Figure 26 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 41. The clock systems are detailed below.
Figure 26. Clock Distribution
Timer/Counter1 |
General I/O |
ADC |
CPU Core |
RAM |
Flash and |
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EEPROM |
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clkADC |
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clkI/O |
AVR Clock |
clkCPU |
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Control Unit |
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clkFLASH |
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Reset Logic |
Watchdog Timer |
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Source clock |
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Watchdog clock |
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Clock |
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Watchdog |
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Multiplexer |
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Oscillator |
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clkPCK |
clkPLL |
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PLL |
External RC |
External clock |
Crystal |
Low-Frequency |
Calibrated RC |
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Oscillator |
Oscillator |
Crystal Oscillator |
Oscillator |
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CPU Clock – clkCPU |
The CPU clock is routed to parts of the system concerned with operation of the AVR |
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core. Examples of such modules are the General Purpose Register File, the Status Reg- |
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ister and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the |
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core from performing general operations and calculations. |
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I/O Clock – clkI/O |
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, and USI. |
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The I/O clock is also used by the External Interrupt module, but note that some external |
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interrupts are detected by asynchronous logic, allowing such interrupts to be detected |
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even if the I/O clock is halted. |
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Flash Clock – clkFLASH |
The Flash clock controls operation of the Flash interface. The Flash clock is usually |
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active simultaneously with the CPU clock. |
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ADC Clock – clkADC |
The ADC is provided with a dedicated clock domain. This allows halting the CPU and |
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I/O clocks in order to reduce noise generated by digital circuitry. This gives more accu- |
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rate ADC conversion results. |
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25 |
1477B–AVR–04/02 |
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Internal PLL for Fast Peripheral Clock Generation – clkPCK
The internal PLL in ATtiny26/L generates a clock frequency that is 64x multiplied from nominally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the internal RC Oscillator which is automatically divided down to 1 MHz, if needed. See the Figure 27 on page 26. When the PLL reference frequency is the nominal 1 MHz, the fast peripheral clock is 64 MHz. The fast peripheral clock, or a clock prescaled from that, can be selected as the clock source for Timer/Counter1.
The PLL is locked on the RC Oscillator and adjusting the RC Oscillator via OSCCAL Register will adjust the fast peripheral clock at the same time. However, even if the possibly divided RC Oscillator is taken to a higher frequency than 1 MHz, the fast peripheral clock frequency saturates at 70 MHz (worst case) and remains oscillating at the maximum frequency. It should be noted that the PLL in this case is not locked any more with the RC Oscillator clock.
Therefore it is recommended not to take the OSCCAL adjustments to a higher frequency than 1 MHz in order to keep the PLL in the correct operating range. The internal PLL is enabled only when the PLLE bit in the register PLLCSR is set or the PLLCK Fuse is programmed (“0”). The bit PLOCK from the register PLLCSR is set when PLL is locked.
Both internal 1 MHz RC Oscillator and PLL are switched off in Power-down and Standby sleep modes.
Figure 27. PCK Clocking System
PLLE |
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PLLCK & |
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CKSEL |
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FUSES |
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OSCCAL |
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Lock |
PLOCK |
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Detector |
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1 |
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PCK |
RC OSCILLATOR |
2 |
DIVIDE |
PLL |
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4 |
TO 1 MHz |
64x |
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8 MHz |
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DIVIDE |
BY 4
CK
XTAL1
OSCILLATORS
XTAL2
26 ATtiny26(L)
1477B–AVR–04/02