
- •Features
- •Pin Configuration
- •Disclaimer
- •Description
- •Pin Descriptions
- •AVCC
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •XTAL1
- •XTAL2
- •SRAM Data Memory
- •I/O Direct
- •Data Direct
- •Data Indirect with Displacement
- •Data Indirect
- •EEPROM Data Memory
- •I/O Memory
- •Status Register – SREG
- •Stack Pointer – SP
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Internal PLL for Fast Peripheral Clock Generation – clkPCK
- •Clock Sources
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Interrupt Handling
- •Interrupt Response Time
- •External Interrupt
- •Pin Change Interrupt
- •Idle Mode
- •ADC Noise Reduction Mode
- •Power-down Mode
- •Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Timer/Counters
- •Timer/Counter0 Prescaler
- •Timer/Counter1 Prescaler
- •8-bit Timer/Counter0
- •Timer/Counter0 – TCNT0
- •8-bit Timer/Counter1
- •Timer/Counter1 – TCNT1
- •Timer/Counter1 in PWM Mode
- •Watchdog Timer
- •Overview
- •Register Descriptions
- •USI Data Register – USIDR
- •USI Status Register – USISR
- •USI Control Register – USICR
- •Functional Descriptions
- •Three-wire Mode
- •SPI Slave Operation Example
- •Two-wire Mode
- •Start Condition Detector
- •Alternative USI Usage
- •4-bit Counter
- •12-bit Timer/Counter
- •Software Interrupt
- •Analog Comparator
- •Analog to Digital Converter
- •Features
- •Operation
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Register Description for I/O Ports
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Clock Drive Waveforms
- •External Clock Drive
- •ADC Characteristics – Preliminary Data
- •ATtiny26/L Register Summary
- •Ordering Information(1)
- •Packaging Information
- •Data Sheet Change Log for ATtiny26
- •Changes from Rev. 1477A-03/02 to Rev. 1477B-04/02
- •Table of Contents

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ATtiny26(L) |
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Electrical Characteristics |
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Absolute Maximum Ratings* |
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Operating Temperature.................................. |
-55°C to +125°C |
*NOTICE: Stresses beyond those listed under “Absolute |
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Maximum Ratings” may cause permanent dam- |
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Storage Temperature ..................................... |
-65°C to +150°C |
age to the device. This is a stress rating only and |
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functional operation of the device at these or |
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Voltage on Any Pin except |
RESET |
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other conditions beyond those indicated in the |
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with Respect to Ground ............................. |
-1.0V to VCC + 0.5V |
operational sections of this specification is not |
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Voltage on |
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with Respect to Ground -1.0V to +13.0V |
implied. Exposure to absolute maximum rating |
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RESET |
conditions for extended periods may affect |
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Maximum Operating Voltage |
6.0V |
device reliability. |
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DC Current per I/O Pin ............................................... |
40.0 mA |
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DC Current VCC and GND Pins ................................ |
200.0 mA |
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DC Characteristics TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted)(1)
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Parameter |
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Condition |
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Min. |
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Typ. |
Max. |
Units |
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VIL |
Input Low Voltage |
Except XTAL1 pin |
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-0.5 |
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0.2VCC |
V |
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VIL1 |
Input Low Voltage |
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XTAL1 pin, External |
-0.5 |
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0.1VCC |
V |
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Clock Selected |
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VIH |
Input High Voltage |
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Except XTAL1 and |
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0.6VCC |
(3) |
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VCC |
+0.5 |
V |
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RESET |
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VIH1 |
Input High Voltage |
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XTAL1 pin, External |
0.8VCC |
(3) |
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VCC |
+0.5 |
V |
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Clock Selected |
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VIH2 |
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(3) |
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Input High Voltage |
RESET pin |
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0.9VCC |
VCC |
+0.5 |
V |
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VOL |
Output Low Voltage(4) |
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IOL = 20 mA, VCC = 5V |
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0.6 |
V |
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(Ports A, B) |
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IOL = 10 mA, VCC = 3V |
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0.5 |
V |
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VOH |
Output High Voltage(5) |
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OH |
= -20 mA, V |
CC |
= 5V |
4.2 |
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V |
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(Ports A, B) |
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IOH = -10 mA, VCC = 3V |
2.3 |
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V |
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IIL |
Input Leakage |
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Vcc = 5.5V, pin low |
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8 |
µA |
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Current I/O Pin |
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(absolute value) |
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IIH |
Input Leakage |
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Vcc = 5.5V, pin high |
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8 |
µA |
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Current I/O Pin |
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(absolute value) |
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RRST |
Reset Pull-up Resistor |
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20 |
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100 |
kΩ |
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Rpu |
I/O Pin Pull-up Resistor |
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20 |
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100 |
kΩ |
125
1477B–AVR–04/02

DC Characteristics T = -40°C to 85°C, V |
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= 2.7V to 5.5V (unless otherwise noted)(1) |
(Continued) |
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A |
CC |
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Symbol |
Parameter |
Condition |
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Min. |
Typ. |
Max. |
Units |
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Active 4 MHz, VCC = 3V |
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6 |
mA |
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(ATtiny26L) |
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Active 8 MHz, VCC = 5V |
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15 |
mA |
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(ATtiny26) |
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Power Supply Current |
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ICC |
Idle 4 MHz, VCC = 3V |
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2 |
mA |
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(ATtiny26L) |
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Idle 8 MHz, VCC = 5V |
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7 |
mA |
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(ATtiny26) |
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Power-down mode(6) |
WDT enabled, VCC = 3V |
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30 |
µA |
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WDT disabled, VCC = 3V |
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10 |
µA |
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VACIO |
Analog Comparator |
VCC = 5V |
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40 |
mV |
Input Offset Voltage |
Vin = VCC/2 |
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IACLK |
Analog Comparator |
VCC = 5V |
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-50 |
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50 |
nA |
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Input Leakage Current |
Vin = VCC/2 |
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tACID |
Analog Comparator |
VCC = 2.7V |
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750 |
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ns |
Propagation Delay |
VCC = 4.0V |
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500 |
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Notes: 1. Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
2.“Max” means the highest value where the pin is guaranteed to be read as low
3.“Min” means the lowest value where the pin is guaranteed to be read as high
4.Although each I/O port can sink more than the test conditions (20mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed:
1] The sum of all IOL, for all ports, should not exceed 400 mA.
2] The sum of all IOL, for port A0 - A7, should not exceed 300 mA. 3] The sum of all IOL, for ports B0 - B7 should not exceed 300 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.
5.Although each I/O port can source more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed:
1] The sum of all IOH, for all ports, should not exceed 400 mA.
2] The sum of all IOH, for port A0 - A7, should not exceed 300 mA. 3] The sum of all IOH, for ports B0 - B7 should not exceed 300 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition.
6.Minimum VCC for Power-down is 2.5V.
126 ATtiny26(L)
1477B–AVR–04/02

ATtiny26(L)
External Clock Drive
Waveforms
External Clock Drive
Figure 70. External Clock Drive Waveforms
VIH1
VIL1
Table 62. External Clock Drive
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VCC = 2.7 - 5.5V |
VCC = 4.5 - 5.5V |
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Symbol |
Parameter |
Min |
Max |
Min |
Max |
Units |
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1/tCLCL |
Oscillator Frequency |
0 |
8 |
0 |
16 |
MHz |
tCLCL |
Clock Period |
125 |
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62.5 |
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tCHCX |
High Time |
50 |
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25 |
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tCLCX |
Low Time |
50 |
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25 |
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tCLCH |
Rise Time |
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1.6 |
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0.5 |
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tCHCL |
Fall Time |
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1.6 |
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0.5 |
s |
127
1477B–AVR–04/02