
- •Features
- •Pin Configuration
- •Disclaimer
- •Description
- •Pin Descriptions
- •AVCC
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •XTAL1
- •XTAL2
- •SRAM Data Memory
- •I/O Direct
- •Data Direct
- •Data Indirect with Displacement
- •Data Indirect
- •EEPROM Data Memory
- •I/O Memory
- •Status Register – SREG
- •Stack Pointer – SP
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Internal PLL for Fast Peripheral Clock Generation – clkPCK
- •Clock Sources
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Interrupt Handling
- •Interrupt Response Time
- •External Interrupt
- •Pin Change Interrupt
- •Idle Mode
- •ADC Noise Reduction Mode
- •Power-down Mode
- •Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Timer/Counters
- •Timer/Counter0 Prescaler
- •Timer/Counter1 Prescaler
- •8-bit Timer/Counter0
- •Timer/Counter0 – TCNT0
- •8-bit Timer/Counter1
- •Timer/Counter1 – TCNT1
- •Timer/Counter1 in PWM Mode
- •Watchdog Timer
- •Overview
- •Register Descriptions
- •USI Data Register – USIDR
- •USI Status Register – USISR
- •USI Control Register – USICR
- •Functional Descriptions
- •Three-wire Mode
- •SPI Slave Operation Example
- •Two-wire Mode
- •Start Condition Detector
- •Alternative USI Usage
- •4-bit Counter
- •12-bit Timer/Counter
- •Software Interrupt
- •Analog Comparator
- •Analog to Digital Converter
- •Features
- •Operation
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Register Description for I/O Ports
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Clock Drive Waveforms
- •External Clock Drive
- •ADC Characteristics – Preliminary Data
- •ATtiny26/L Register Summary
- •Ordering Information(1)
- •Packaging Information
- •Data Sheet Change Log for ATtiny26
- •Changes from Rev. 1477A-03/02 to Rev. 1477B-04/02
- •Table of Contents

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ATtiny26(L) |
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Fuse Bits |
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The ATtiny26 has two Fuse bytes. Table 49 and Table 50 describe briefly the functional- |
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ity of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are |
read as logical zero, “0”, if they are programmed.
Table 49. Fuse High Byte
Fuse High Byte |
Bit No |
Description |
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Default Value |
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7 |
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– |
1 |
(unprogrammed) |
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6 |
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– |
1 |
(unprogrammed) |
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5 |
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– |
1 |
(unprogrammed) |
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RSTDISBL |
4 |
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Select if PB7 is I/O pin or |
1 |
(unprogrammed, PB7 is |
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RESET pin |
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RESET pin) |
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SPIEN(1) |
3 |
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Enable Serial Program |
0 |
(programmed, SPI prog. |
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and Data Downloading |
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enabled) |
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EEPROM memory is |
1 |
(unprogrammed, EEPROM not |
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EESAVE |
2 |
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preserved through the Chip |
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preserved) |
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Erase |
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BODLEVEL |
1 |
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Brown out detector trigger |
1 |
(unprogrammed) |
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level |
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BODEN |
0 |
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1 |
(unprogrammed, BOD |
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Brown out detector enable |
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disabled) |
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Note: 1. The SPIEN Fuse is not accessible in serial programming mode. |
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Table 50. Fuse Low Byte |
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Fuse Low Byte |
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Bit No |
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Description |
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Default Value |
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PLLCK |
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7 |
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Use PLL for internal clock |
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1 |
(unprogrammed) |
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CKOPT(3) |
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6 |
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Oscillator options |
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1 |
(unprogrammed) |
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SUT1 |
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5 |
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Select start-up time |
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1 |
(unprogrammed)(1) |
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SUT0 |
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4 |
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Select start-up time |
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0 |
(programmed)(1) |
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CKSEL3 |
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3 |
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Select Clock source |
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0 |
(programmed)(2) |
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CKSEL2 |
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2 |
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Select Clock source |
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0 |
(programmed)(2) |
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CKSEL1 |
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1 |
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Select Clock source |
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0 |
(programmed)(2) |
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CKSEL0 |
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0 |
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Select Clock source |
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1 |
(unprogrammed)(2) |
Notes: 1. The default value of SUT1..0 results in maximum start-up time. See Table 13 on page 31 for details.
2.The default setting of CKSEL3..0 results in internal RC Oscillator at 1 MHz. See Table 4 on page 27 for details.
3.The CKOPT Fuse functionality depends on the setting of the CKSEL bits. See “System Clock and Clock Options” on page 25 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
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1477B–AVR–04/02