
- •Features
- •Pin Configuration
- •Disclaimer
- •Description
- •Pin Descriptions
- •AVCC
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •XTAL1
- •XTAL2
- •SRAM Data Memory
- •I/O Direct
- •Data Direct
- •Data Indirect with Displacement
- •Data Indirect
- •EEPROM Data Memory
- •I/O Memory
- •Status Register – SREG
- •Stack Pointer – SP
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Internal PLL for Fast Peripheral Clock Generation – clkPCK
- •Clock Sources
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Interrupt Handling
- •Interrupt Response Time
- •External Interrupt
- •Pin Change Interrupt
- •Idle Mode
- •ADC Noise Reduction Mode
- •Power-down Mode
- •Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Timer/Counters
- •Timer/Counter0 Prescaler
- •Timer/Counter1 Prescaler
- •8-bit Timer/Counter0
- •Timer/Counter0 – TCNT0
- •8-bit Timer/Counter1
- •Timer/Counter1 – TCNT1
- •Timer/Counter1 in PWM Mode
- •Watchdog Timer
- •Overview
- •Register Descriptions
- •USI Data Register – USIDR
- •USI Status Register – USISR
- •USI Control Register – USICR
- •Functional Descriptions
- •Three-wire Mode
- •SPI Slave Operation Example
- •Two-wire Mode
- •Start Condition Detector
- •Alternative USI Usage
- •4-bit Counter
- •12-bit Timer/Counter
- •Software Interrupt
- •Analog Comparator
- •Analog to Digital Converter
- •Features
- •Operation
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Register Description for I/O Ports
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Clock Drive Waveforms
- •External Clock Drive
- •ADC Characteristics – Preliminary Data
- •ATtiny26/L Register Summary
- •Ordering Information(1)
- •Packaging Information
- •Data Sheet Change Log for ATtiny26
- •Changes from Rev. 1477A-03/02 to Rev. 1477B-04/02
- •Table of Contents

Pin Configuration
PDIP/SOIC/SSOP
|
|
|
|
|
|
|
(MOSI/DI/SDA/OC1A) PB0 |
1 |
20 |
PA0 (ADC0) |
|||
(MISO/DO/OC1A) PB1 |
2 |
19 |
PA1 (ADC1) |
|||
|
|
|
3 |
18 |
PA2 (ADC2) |
|
(SCK/SCL/OC1B) |
PB2 |
|||||
|
(OC1B) PB3 |
4 |
17 |
PA3 (AREF) |
||
|
|
|
VCC |
5 |
16 |
GND |
|
|
|
GND |
6 |
15 |
AVCC |
(ADC7/XTAL1) PB4 |
7 |
14 |
PA4 (ADC3) |
|||
(ADC8/XTAL2) PB5 |
8 |
13 |
PA5 (ADC4) |
|||
(ADC9/INT0/T0) PB6 |
9 |
12 |
PA6 (ADC5/AIN0) |
|||
|
|
|
|
10 |
11 |
PA7 (ADC6/AIN1) |
(ADC10/RESET) |
PB7 |
|||||
|
|
|
|
|
|
|
NC 1 (OC1B) PB3
2 NC
3 VCC
4 GND
5 NC
6
(ADC7/XTAL1) PB4 7 (ADC8/XTAL2) PB5
8
MLF Top View
PB2 (SCK/SCL/OC1B) |
PB1 (MISO/DO/OC1A) |
|
PB0 (MOSI/DI/SDA/OC1A) |
NC |
NC |
NC |
PA0 (ADC0) |
PA1 (ADC1) |
|
||||||||
|
||||||||
32 |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
|
NC |
PB6 |
|
PB7 |
NC |
PA7 |
PA6 |
PA5 |
NC |
|
(ADC9/INT0/T0) |
|
(ADC10/RESET) |
|
(ADC6/AIN1) |
(ADC5/AIN0) |
(ADC4) |
|
|
|
|
|
|||||
|
|
|
|
|
24 NC
23 PA2 (ADC2)
22 PA3 (AREF)
21 GND
20 NC
19 NC
18 AVCC
17 PA4 (ADC3)
Disclaimer |
Typical values contained in this data sheet are based on simulations and characteriza- |
|
tion of other AVR microcontrollers manufactured on the same process technology. Min |
|
and Max values will be available after the device is characterized. |
2 ATtiny26(L)
1477B–AVR–04/02