
- •Features
- •Pin Configuration
- •Disclaimer
- •Description
- •Pin Descriptions
- •AVCC
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •XTAL1
- •XTAL2
- •SRAM Data Memory
- •I/O Direct
- •Data Direct
- •Data Indirect with Displacement
- •Data Indirect
- •EEPROM Data Memory
- •I/O Memory
- •Status Register – SREG
- •Stack Pointer – SP
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Clock Systems and their Distribution
- •CPU Clock – clkCPU
- •I/O Clock – clkI/O
- •Flash Clock – clkFLASH
- •ADC Clock – clkADC
- •Internal PLL for Fast Peripheral Clock Generation – clkPCK
- •Clock Sources
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Interrupt Handling
- •Interrupt Response Time
- •External Interrupt
- •Pin Change Interrupt
- •Idle Mode
- •ADC Noise Reduction Mode
- •Power-down Mode
- •Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Timer/Counters
- •Timer/Counter0 Prescaler
- •Timer/Counter1 Prescaler
- •8-bit Timer/Counter0
- •Timer/Counter0 – TCNT0
- •8-bit Timer/Counter1
- •Timer/Counter1 – TCNT1
- •Timer/Counter1 in PWM Mode
- •Watchdog Timer
- •Overview
- •Register Descriptions
- •USI Data Register – USIDR
- •USI Status Register – USISR
- •USI Control Register – USICR
- •Functional Descriptions
- •Three-wire Mode
- •SPI Slave Operation Example
- •Two-wire Mode
- •Start Condition Detector
- •Alternative USI Usage
- •4-bit Counter
- •12-bit Timer/Counter
- •Software Interrupt
- •Analog Comparator
- •Analog to Digital Converter
- •Features
- •Operation
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions Of Port B
- •Register Description for I/O Ports
- •Port A Data Register – PORTA
- •Port B Data Register – PORTB
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •External Clock Drive Waveforms
- •External Clock Drive
- •ADC Characteristics – Preliminary Data
- •ATtiny26/L Register Summary
- •Ordering Information(1)
- •Packaging Information
- •Data Sheet Change Log for ATtiny26
- •Changes from Rev. 1477A-03/02 to Rev. 1477B-04/02
- •Table of Contents

Timer/Counter1
Prescaler
8-bit Timer/Counter0
1477B–AVR–04/02
ATtiny26(L)
Figure 32 shows the Timer/Counter1 prescaler. For Timer/Counter1 the clock selections are between PCK to PCK/16384 and stop in asynchronous mode and CK to CK/16384 and stop in synchronous. The clock options are described in Table 24 on page 52 and the Timer/Counter1 Control Register, TCCR1B. Setting the PSR1 bit in TCCR1B Register resets the prescaler. The PCKE bit in the PLLCSR Register enables the asynchronous mode.
Figure 32. Timer/Counter1 Prescaler
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PCKE |
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PSR1 |
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CK |
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T1CK |
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S |
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14-BIT |
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PCK |
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A |
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T/C PRESCALER |
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T1CK/2 |
T1CK/4 |
T1CK/8 |
T1CK/16 |
T1CK/32 |
T1CK/64 |
T1CK/128 |
T1CK/256 |
T1CK/512 |
T1CK/1024 |
T1CK/2048 |
T1CK/4096 |
T1CK/8192 |
T1CK/16384 |
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0 |
T1CK |
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CS10
CS11
CS12
CS13
TIMER/COUNTER1 COUNT ENABLE
Figure 33 shows the block diagram for Timer/Counter0.
The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition, it can be stopped as described in the specification for the Timer/Counter0 Control Register – TCCR0. The overflow status flag is found in the Timer/Counter Interrupt Flag Register – TIFR. Control signals are found in the Timer/Counter0 Control Register – TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register – TIMSK.
When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To ensure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock.
The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions.
45

Figure 33. Timer/Counter0 Block Diagram
Timer/Counter0 Control
Register – TCCR0
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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$33 ($53) |
– |
– |
– |
– |
PSR0 |
CS02 |
CS01 |
CS00 |
TCCR0 |
Read/Write |
R |
R |
R |
R |
R/W |
R/W |
R/W |
R/W |
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Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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• Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26/L and always read as zero.
• Bit 3 – PSR0: Prescaler Reset Timer/Counter0
When this bit is set (one), the prescaler of the Timer/Counter0 will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero.
46 ATtiny26(L)
1477B–AVR–04/02