External Interrupt

The External Interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt

will trigger even if the INT0 pin is configured as an output. This feature provides a way of

generating a software interrupt. The External Interrupt can be triggered by a falling or

rising edge, a pin change, or a low level. This is set up as indicated in the specification

for the MCU Control Register – MCUCR. When the External Interrupt is enabled and is

configured as level triggered, the interrupt will trigger as long as the pin is held low.

Pin Change Interrupt

The pin change interrupt is triggered by any change on any I/O pin of Port B and pins

PA3, PA6, and PA7, if the interrupt is enabled and alternate function of the pin does not

mask out the interrupt. The bit PCIE1 in GIMSK enables interrupt from pins PB[7:4],

PA[7:6], and PA[3]. PCIE0 enables interrupt on digital pins PB[3:0].

The pin change interrupt is different from other interrupts in two ways. First, pin change

interrupt enable bits PCIE1 and PCIE0 also mask the flag if they are not set. The normal

operation on most interrupts is that the flag is always active and only the execution of

the interrupt is masked by the interrupt enable.

Secondly, please note that pin change interrupt is disabled for any pin that is configured

as an alternate function. For example, no pin change interrupt is generated from pins

that are configured as AREF, AIN0 or AIN1, OC1A,

OC1A,

OC1B,

OC1B,

XTAL1, or

XTAL2 in a fuse selected clock option, Timer0 clocking, or

RESET

function. See Table

17 for alternate functions which mask the pin change interrupt and how the function is

enabled. For example pin change interrupt on the PB0 is disabled when USI Two-wire

mode or USI Three-wire mode or Timer/Counter1 inverted output compare is enabled.

If the interrupt is enabled, the interrupt will trigger even if the changing pin is configured

as an output. This feature provides a way of generating a software interrupt. Also

observe that the pin change interrupt will trigger even if the pin activity triggers another

interrupt, for example the external interrupt. This implies that one external event might

cause several interrupts.

The value of the programmed fuse is “0” and unprogrammed is “1”. Each of the lines

enables the alternate function so “or” function of the lines enables the function.

Table 17. Alternative Functions

Control Register[Bit Name] which

Bit or Fuse

Pin

Alternate Function

set the Alternate Function(1)

Value(2)

PA3

AREF

ADMUX[REFS0]

1

PA6

Analog Comparator

ACSR[ACD]

0

PA7

Analog Comparator

ACSR[ACD]

0

PB0

USI Two-wire mode

USICR[USIWM1]

1

USI Three-wire mode

USICR[USIWM1,USIWM0]

01

TC1 compare/PWM

TCCR1A[COM1A1,COM1A0,PWM1A]

011

PB1

USI Three-wire mode

USICR[USIWM1,USIWM0]

01

TC1 compare/PWM

TCCR1A[COM1A1]

1

TCCR1A[COM1A0]

1

PB2

USI Two-wire mode

USICR[USIWM1]

1

USI Three-wire mode

USICR[USIWM1,USIWM0]

01

TC1 compare/PWM

TCCR1A[COM1B1,COM1B0,PWM1B]

011

PB3

TC1 compare/PWM

TCCR1A[COM1B1]

1

TCCR1A[COM1B0]

1

ATtiny26(L)

Table 17. Alternative Functions

(Continued)

Control Register[Bit Name] which

Bit or Fuse

Pin

Alternate Function

set the Alternate Function(1)

Value(2)

PB4

XTAL1, clock source

FUSE[PLLCK,CKSEL]

10000

FUSE[PLLCK,CKSEL]

10101-11111

PB5

XTAL2, clock source

FUSE[PLLCK,CKSEL]

11001-11111

PB6

External interrupt

GIMSK[INT0],MCUCR[ISC01,ISC01]

100

TC0 clock

TCCR0[CS02,CS01]

11

PB7

RESET

RSTDISBL FUSE

1

MCU Control Register –

The MCU Control Register contains control bits for general MCU functions.

MCUCR

Bit

7

6

5

4

3

2

1

0

$35 ($55)

–

PUD

SE

SM1

SM0

–

ISC01

ISC00

MCUCR

Read/Write

R

R/W

R/W

R/W

R/W

R

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

Table 18.

Sleep Modes

SM1

SM0

Sleep Mode

0

0

Idle mode

0

1

ADC Noise Reduction mode

1

0

Power-down mode

1

1

Standby mode

ISC01

ISC00

Description

0

0

The low level of INT0 generates an interrupt request.

0

1

Any change on INT0 generates an interrupt request.

1

0

The falling edge of INT0 generates an interrupt request.

1

1

The rising edge of INT0 generates an interrupt request.

ATtiny26(L)

Power Management

Sleep modes enable the application to shut down unused modules in the MCU, thereby

and Sleep Modes

saving power. The AVR provides various sleep modes allowing the user to tailor the

power consumption to the application’s requirements.

To enter any of the four sleep modes, the SE bit in MCUCR must be written to logic one

and a SLEEP instruction must be executed. The SM1, and SM0 bits in the MCUCR

Register select which sleep mode (Idle, ADC Noise Reduction, Power Down, or Stand-

by) will be activated by the SLEEP instruction. See Table 18 for a summary. If an

enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The

MCU is then halted for four cycles in addition to the start-up time, it executes the inter-

rupt routine, and resumes execution from the instruction following SLEEP. The contents

of the Register File and SRAM are unaltered when the device wakes up from sleep. If a

Reset occurs during sleep mode, the MCU wakes up and executes from the Reset

Vector.

Table 20 on page 42 presents the different clock systems in the ATtiny26, and their dis-

tribution. The figure is helpful in selecting an appropriate sleep mode.

Idle Mode

When the SM1..0 bits are written to “00”, the SLEEP instruction makes the MCU enter

Idle mode, stopping the CPU but allowing Analog Comparator, ADC, USI,

Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep

mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as

internal ones like the Timer Overflow and USI Start and Overflow interrupts. If wake-up

from the Analog Comparator interrupt is not required, the Analog Comparator can be

powered down by setting the ACD bit in the Analog Comparator Control and Status

Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is

enabled, a conversion starts automatically when this mode is entered.

ADC Noise Reduction Mode

When the SM1..0 bits are written to “01”, the SLEEP instruction makes the MCU enter

ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the External Inter-

rupts, the USI start condition detection, and the Watchdog to continue operating (if

enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the

other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measure-

ments. If the ADC is enabled, a conversion starts automatically when this mode is

entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a

Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an EEPROM ready

interrupt, an External Level Interrupt on INT0, or a pin change interrupt can wake up the

MCU from ADC Noise Reduction mode.

Power-down Mode

When the SM1..0 bits are written to “10”, the SLEEP instruction makes the MCU enter

Power-down mode. In this mode, the External Oscillator is stopped, while the External

Interrupts, the USI start condition detection, and the Watchdog continue operating (if

enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, USI start con-

dition interrupt, an External Level Interrupt on INT0, or a pin change interrupt can wake

up the MCU. This sleep mode basically halts all generated clocks, allowing operation of

asynchronous modules only.

When waking up from Power-down mode, there is a delay from the wake-up condition

occurs until the wake-up becomes effective. This allows the clock to restart and become

stable after having been stopped. The wake-up period is defined by the same CKSEL

Fuses that define the reset time-out period, as described in “Clock Sources” on page 27.

41

1477B–AVR–04/02