Digital switching fields. Construction and operation principles of space switching unit (ssu) with parameters 2×4×6 built upon мх.
Digital switching fields. Construction and operation principles of space switching unit (ssu) with parameters 2×4×6 built upon dмх.
Digital switching fields. Construction and operation principles of time switching unit (tsu) with parameters 1×8×8. Control modes in tsu.
The process of information transfer from one time channel to another within the same line is known as time switching.
The switching units of TS type are the most common for modern digital switching systems. It is necessary to backup digital switching networks in order to increase system’s reliability. The main DSN and backup DSN operate in turns. In the case of malfunction one of the DSNs operates and subscribers don’t even know about the problem
Time switching of digital channels
Time switching means time shift of code words. The following figure shows the process of time switching.
Cycle Cycle
IL
OL
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Figure 18 – Time switching
If i < j then it is possible to transfer information within one cycle. In this case delay is td = j – i (TC).
If i > j then it is impossible to transfer information within one cycle. The information is going to be transferred during the next cycle. In this case delay is
td = n – j + i (TC).
It is possible to construct a time switching unit using delay elements. These elements are also known as shift elements. Such a time switch includes n – 1 delay cells connected sequentially. Every such cell can store r digits. Every cell delays information for one time channel.
Control memory of the switch consists of n memory cells according to the quantity of handled TCs.
Il ol g c o u n t e r cm cell- cm cell- cm cell- cm cell- Controller
Figure 19 – Time switch with delay elements
If it is necessary to connect the same TCs of lines then information is going to transit 0 AND element which means no delay. In this case it is necessary to write the address of 0 AND element to an appropriate memory cell.
If for example it is necessary to connect TC-3 with TC-8 then it is necessary to calculate delay value first.
td = 8 – 3 = 5 TCs
In this case it is necessary to write the address of 5-th AND element to the 8-th memory cell. During the 8-th time channel the 8-th memory cell of CM will be read. Its content will open the 5-th AND element creating the switching path.
A time switch can be built upon memory elements. In this case, information is written to the cells of information memory in one order and read out in another. Switch of such type require buffer registers at input and output. These registers convert information from sequential code to the parallel form. And of course the switch operates using the parallel code.
Such a time switch can operate either in mode 1 or in mode 2.
Mode 1 Writing of the code words from the input line to the IM is performed with the random access to the cells according to the addresses obtained from CM. In this mode the code words are read out to the output lines with the sequential access to the cells.
Mode 2 Writing of the code words from the input line to the IM is performed with the sequential access to the cells. And the code words are read out to the output lines with the random access to the cells according to the addresses obtained from CM.
Writing and reading of information is performed in the parallel code in order to increase quantity of served channels. There is the register at the TSU’s input. This register converts incoming information from the sequential code to the parallel. There is the output register at the output of IM. The information converted to the sequential form goes to the output line from the output register.
IM cells: n = 8; r = 8
CM cells: n = 8; r = 4
4
Figure 20 – Time switch
Memory characteristics
Quantity of the necessary IM cells coincides with the quantity of time channels (n) handled. Digit capacity of every IM cell equals the quantity of samples within a time channel (r).
Control memory is arranged in one section having n memory cells. . Control memory has as many cells as IM does. Digit capacity of every CM cell: CB+log2n, where n – quantity of IM cells = quantity of time channels.