Diagram comparing classifications

Visually, these four architectures are shown below where each "PU" is a processing unit:

Further divisions

As of 2006, all the top 10 and most of the TOP500 supercomputers are based on a MIMD architecture.

Single Program, Multiple Data (SPMD)

Multiple autonomous processors simultaneously executing the same program (but at independent points, rather than in the lockstep that SIMD imposes) on different data. Also referred to as 'Single Process, multiple data'. SPMD is the most common style of parallel programming. The term was originally coined by Gregory F. Pfister.

Multiple Program Multiple Data (MPMD)

Multiple autonomous processors simultaneously operating at least 2 independent programs. Typically such systems pick one node to be the "host" ("the explicit host/node programming model") or "manager" (the "Manager/Worker" strategy), which runs one program that farms out data to all the other nodes which all run a second program. Those other nodes then return their results directly to the manager. An example of this would be the Sony Playstation 3 game console, with its SPU/PPU processor architecture.

The basic concepts of architecture of the high-efficiency computing systems.

The architecture of traditional consecutive computers is based on John Fon Neumann's ideas and also includes the central processor, RAM - address space with linear addressing and the control block. Sequence of commands is applied to sequence of the data. Speed of such traditional computer is defined by speed of its central processor and access time to RAM. Speed of the central processor can be increased by increasing of frequency which size depends on density of elements in the integrated scheme, a way of their "packing" and speed of RAM microcircuits.

Other methods of speed increase are based on expansion of traditional Neumann's architecture:

– usage of RISC processors, that is processors with the reduced set of commands. In RISC processors the most part of commands is carried out for 1-2 steps;

– usage of superscalar processors;

– usage of conveyors.

In high-efficiency computing systems are used both traditional architectural elements, and its expansions, and also new elements, such, for example, as vector processors etc. In this section we will consider such major concepts of organizations of high-efficiency computing systems, as vector data processing , conveyors, methods and types of interprocessor communications, the RAM organization.

Vector Processing

Processing of sequences of data in a uniform manner, a common occurrence in manipulation of matrices (whose elements are vectors) or other arrays of data. A vector processor will process sequences of input data as a result of obeying a single vector instruction and generate a result data sequence. 

A vector processor is a processor that can operate on entire vectors with one instruction, i.e. the operands of some instructions specify complete vectors.

The vector processor "is able" to process one command not one value, but vector (array) of values. Let A1, A2 and P are the three vectors having the same dimension and length, also there is an operator P=A1+A2.

The vector processor for one cycle of performance of a command will execute paired addition of vector elements A1 and A2 and also will appropriate the received values to corresponding elements of vector P. Each operand is thus stored in the special, vector register. The consecutive processor should carry out addition operation several times for elements of two vectors. The vector processor executes only one command! Certainly, realization of such command will be more difficult.