TIMING EXAMPLES

Figure 6 and Figure 7 show some of the timing parameters from the Timing Specifications section.

Timing Example 1

As shown in Figure 7, when fSCLK = 5 MHz and the throughput is 250 kSPS, the cycle time is

t2 + 12.5(1/fSCLK) + tACQ = 4 µs

With t2 = 10 ns minimum, then tACQ is 1.49 µs, which satisfies the requirement of 290 ns for tACQ.

In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where t10 = 30 ns maximum. This allows a value of 960 ns for tQUIET, satisfying the minimum requirement of 30 ns.

Timing Example 2

The AD7921 can also operate with slower clock frequencies. As shown in Figure 7, when fSCLK = 2 MHz and the throughput rate is 100 KSPS, the cycle time is

t2 + 12.5(1/fSCLK) + tACQ = 10 µs

With t2 = 10 ns minimum, then tACQ is 3.74 µs, which satisfies the requirement of 290 ns for tACQ.

In Figure 7, tACQ is comprised of 2.5(1/fSCLK) + t10 + tQUIET, where t10 = 30 ns maximum. This allows a value of 2.46 µs for tQUIET, satisfying the minimum requirement of 30 ns.

In this example, as with other slower clock values, the signal might already be acquired before the conversion is complete, but it is still necessary to leave 30 ns minimum tQUIET between conversions. In this example, the signal should be fully acquired at approximately point C in Figure 7.

Figure 6. AD7921 Serial Interface Timing Diagram

Figure 7. Serial Interface Timing Example

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