strap mode, the interrupt vectors are directed to RAM. This allows the use of interrupts through a jump table. Refer to Motorola application note AN1060, M68HC11 Bootstrap
Mode.
4.2 Memory Map
The operating mode determines memory mapping and whether external addresses can be accessed. Refer to Figure 4-2, Figure 4-3, and Figure 4-4, which illustrate the memory maps for each of the three families comprising the M68HC11 E series of
MCUs. Memory locations for on-chip resources are the same for both expanded and single-chip modes. Control bits in the CONFIG register allow EPROM and EEPROM (if present) to be disabled from the memory map. The RAM is mapped to $0000 after reset. It can be placed at any 4-Kbyte boundary ($x000) by writing an appropriate value to the INIT register. The 64-byte register block is mapped to $1000 after reset and can also be placed at any 4-Kbyte boundary ($x000) by writing an appropriate value to the INIT register. If RAM and registers are mapped to the same boundary, the first 64 bytes of RAM will be inaccessible. Refer to Table 4-1, which details the MCU reg-
ister and control bit assignments. 4
$0000 |
|
0000 |
|
EXT |
EXT |
|
512 BYTES RAM |
01FF |
|
||
|
|
|
|
$1000 |
|
1000 |
64-BYTE REGISTER BLOCK |
|
|
||
|
|
|
|
EXT |
EXT |
103F |
|
|
|
||
|
|
B600 |
512 BYTES EEPROM |
$B600 |
|
|
B7FF |
|
|
|
|
EXT |
|
BF00 |
BOOT |
BFC0 |
SPECIAL MODES |
|
|
EXT |
ROM |
|
INTERRUPT |
|
|
|
|
|
|
|
|
|
|
|
BFFF |
|
BFFF |
VECTORS |
|
|
|
|
|
||
$D000 |
|
|
D000 |
12 KBYTES ROM/EPROM |
|
|
|
|
|
|
|
FFC0 |
NORMAL |
|
|
|
|
|
|
MODES |
|
|
|
|
|
FFFF |
INTERRUPT |
$FFFF |
|
|
FFFF |
|
VECTORS |
|
SINGLE |
EXPANDED |
BOOTSTRAP |
SPECIAL |
|
|
|
CHIP |
|
|
TEST |
|
|
|
E SERIES MEM MAP P1
Figure 4-2 Memory Map for MC68HC11E0, MC68HC11E1, MC68HC11E8, and MC68HC(7)11E9
M68HC11 E SERIES |
OPERATING MODES AND ON-CHIP MEMORY |
MOTOROLA |
TECHNICAL DATA |
|
4-3 |
|
$0000 |
|
|
|
0000 |
768 BYTES RAM |
|
|
|
|
EXT |
|
EXT |
|
|
|
|
|
|
|
02FF |
|
|
|
||
|
|
|
|
|
|
|
|
|
|
$1000 |
|
|
|
1000 |
64-BYTE REGISTER BLOCK |
||
|
|
|
|
|
|
|||
|
|
EXT |
|
EXT |
103F |
|
|
|
|
|
|
|
|
|
|
||
|
$9000 |
|
|
|
9000 |
8 KBYTES ROM/EPROM * |
|
|
|
|
|
|
AFFF |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
EXT |
|
EXT |
B600 |
512 BYTES EEPROM |
|
|
|
$B600 |
|
|
|
B7FF |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
EXT |
|
EXT |
BF00 |
BOOT |
BFC0 |
SPECIAL MODES |
|
|
|
|
ROM |
|
INTERRUPT |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BFFF |
|
BFFF |
VECTORS |
|
|
|
|
|
|
|
||
|
$D000 |
|
|
|
D000 |
12 KBYTES ROM/EPROM * |
||
4 |
|
|
|
|
|
|
FFC0 |
NORMAL |
|
|
|
|
|
|
|
MODES |
|
|
|
|
|
|
|
|
INTERRUPT |
|
$FFFF |
|
|
|
FFFF |
|
FFFF |
VECTORS |
|
SINGLE |
EXPANDED |
BOOTSTRAP |
SPECIAL |
|
|
|
|
|
CHIP |
|
|
TEST |
|
|
|
|
|
* 20 KBYTES ROM/EPROM ARE CONTAINED IN TWO SEGMENTS OF 8 KBYTES AND 12 KBYTES EACH.
E SERIES MEM MAP P2
Figure 4-3 Memory Map for MC68HC(7)11E20
MOTOROLA |
OPERATING MODES AND ON-CHIP MEMORY |
M68HC11 E SERIES |
4-4 |
|
TECHNICAL DATA |
$0000 |
|
|
|
0000 |
256 BYTES RAM |
|
|
|
|
|
|
EXT |
|
|
|
|
|
|
EXT |
|
00FF |
|
|
|
|
|
$1000 |
|
|
|
1000 |
64-BYTE REGISTER BLOCK |
|
||
|
|
|
|
|
||||
|
|
|
|
|
|
|||
|
|
|
|
103F |
|
|
|
|
|
EXT |
|
EXT |
|
|
|
|
|
|
|
|
|
BF00 |
BOOT |
BFC0 |
SPECIAL MODES |
|
|
|
|
|
|
ROM |
|
INTERRUPT |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BFFF |
|
BFFF |
VECTORS |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
2048 BYTES EEPROM |
|
|
|
$F800 |
|
|
|
F800 |
|
FFC0 |
NORMAL |
4 |
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
MODES |
|
|
|
|
|
|
|
|
INTERRUPT |
|
$FFFF |
|
|
|
FFFF |
|
FFFF |
VECTORS |
|
SINGLE |
EXPANDED |
BOOTSTRAP |
SPECIAL |
|
|
|
|
|
CHIP |
|
|
TEST |
|
|
|
|
|
|
|
|
|
|
|
|
E SERIES MEM MAP P3 |
|
Figure 4-4 Memory Map for MC68HC811E2
M68HC11 E SERIES |
OPERATING MODES AND ON-CHIP MEMORY |
MOTOROLA |
TECHNICAL DATA |
|
4-5 |
Table 4-1 Register and Control Bit Assignments
|
|
|
The register block can be remapped to any 4K boundary |
|
|
||||||
|
|
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit 0 |
|
|
|
$1000 |
|
|
|
|
|
|
|
|
|
PORTA |
|
PA7 |
PA6 |
|
PA5 |
PA4 |
PA3 |
PA2 |
PA1 |
PA0 |
||
|
$1001 |
|
|
|
|
|
|
|
|
|
Reserved |
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
||
|
$1002 |
|
|
|
|
|
|
|
|
|
PIOC |
|
STAF |
STAI |
|
CWOM |
HNDS |
OIN |
PLS |
EGA |
INVB |
||
|
$1003 |
|
|
|
|
|
|
|
|
|
PORTC |
|
|
|
|
|
|
|
|
|
|
||
|
PC7 |
PC6 |
|
PC5 |
PC4 |
PC3 |
PC2 |
PC1 |
PC0 |
||
|
$1004 |
|
|
|
|
|
|
|
|
|
PORTB |
|
|
|
|
|
|
|
|
|
|
||
|
PB7 |
PB6 |
|
PB5 |
PB4 |
PB3 |
PB2 |
PB1 |
PB0 |
||
|
$1005 |
|
|
|
|
|
|
|
|
|
PORTCL |
|
|
|
|
|
|
|
|
|
|
||
|
PCL7 |
PCL6 |
|
PCL5 |
PCL4 |
PCL3 |
PCL2 |
PCL1 |
PCL0 |
||
4 |
$1006 |
|
|
|
|
|
|
|
|
|
Reserved |
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|||
$1007 |
|
|
|
|
|
|
|
|
|
DDRC |
|
DDC7 |
DDC6 |
|
DDC5 |
DDC4 |
DDC3 |
DDC2 |
DDC1 |
DDC0 |
|||
$1008 |
|
|
|
|
|
|
|
|
|
PORTD |
|
|
|
|
|
|
|
|
|
|
|||
0 |
0 |
|
PD5 |
PD4 |
PD3 |
PD2 |
PD1 |
PD0 |
|||
$1009 |
|
|
|
|
|
|
|
|
|
DDRD |
|
|
0 |
0 |
|
DDD5 |
DDD4 |
DDD3 |
DDD2 |
DDD1 |
DDD0 |
||
|
$100A |
|
|
|
|
|
|
|
|
|
PORTE |
|
|
|
|
|
|
|
|
|
|
||
|
PE7 |
PE6 |
|
PE5 |
PE4 |
PE3 |
PE2 |
PE1 |
PE0 |
||
|
$100B |
|
|
|
|
|
|
|
|
|
CFORC |
|
|
|
|
|
|
|
|
|
|
||
|
FOC1 |
FOC2 |
|
FOC3 |
FOC4 |
FOC5 |
0 |
0 |
0 |
||
|
$100C |
|
|
|
|
|
|
|
|
|
OC1M |
|
|
|
|
|
|
|
|
|
|
||
|
OC1M7 |
OC1M6 |
|
OC1M5 |
OC1M4 |
OC1M3 |
0 |
0 |
0 |
||
|
$100D |
|
|
|
|
|
|
|
|
|
OC1D |
|
|
|
|
|
|
|
|
|
|
||
|
OC1D7 |
OC1D6 |
|
OC1D5 |
OC1D4 |
OC1D3 |
0 |
0 |
0 |
||
|
$100E |
|
|
|
|
|
|
|
|
|
TCNT (High) |
|
|
|
|
|
|
|
|
|
|
||
|
Bit 15 |
14 |
|
13 |
12 |
11 |
10 |
9 |
Bit 8 |
||
|
$100F |
|
|
|
|
|
|
|
|
|
TCNT (Low) |
|
|
|
|
|
|
|
|
|
|
||
|
Bit 7 |
6 |
|
5 |
4 |
3 |
2 |
1 |
Bit 0 |
||
|
$1010 |
|
|
|
|
|
|
|
|
|
TIC1 (High) |
|
|
|
|
|
|
|
|
|
|
||
|
Bit 15 |
14 |
|
13 |
12 |
11 |
10 |
9 |
Bit 8 |
||
|
$1011 |
|
|
|
|
|
|
|
|
|
TIC1 (Low) |
|
|
|
|
|
|
|
|
|
|
||
|
Bit 7 |
6 |
|
5 |
4 |
3 |
2 |
1 |
Bit 0 |
||
|
$1012 |
|
|
|
|
|
|
|
|
|
TIC2 (High) |
|
|
|
|
|
|
|
|
|
|
||
|
Bit 15 |
14 |
|
13 |
12 |
11 |
10 |
9 |
Bit 8 |
||
|
$1013 |
|
|
|
|
|
|
|
|
|
TIC2 (Low) |
|
|
|
|
|
|
|
|
|
|
||
|
Bit 7 |
6 |
|
5 |
4 |
3 |
2 |
1 |
Bit 0 |
||
|
$1014 |
|
|
|
|
|
|
|
|
|
TIC3 (High) |
|
|
|
|
|
|
|
|
|
|
||
|
Bit 15 |
14 |
|
13 |
12 |
11 |
10 |
9 |
Bit 8 |
||
|
$1015 |
|
|
|
|
|
|
|
|
|
TIC3 (Low) |
|
|
|
|
|
|
|
|
|
|
||
|
Bit 7 |
6 |
|
5 |
4 |
3 |
2 |
1 |
Bit 0 |
||
|
$1016 |
|
|
|
|
|
|
|
|
|
TOC1 (High) |
|
|
|
|
|
|
|
|
|
|
||
|
Bit 15 |
14 |
|
13 |
12 |
11 |
10 |
9 |
Bit 8 |
||
|
$1017 |
|
|
|
|
|
|
|
|
|
TOC1 (Low) |
|
|
|
|
|
|
|
|
|
|
||
|
Bit 7 |
6 |
|
5 |
4 |
3 |
2 |
1 |
Bit 0 |
||
|
$1018 |
|
|
|
|
|
|
|
|
|
TOC2 (High) |
|
|
|
|
|
|
|
|
|
|
||
|
Bit 15 |
14 |
|
13 |
12 |
11 |
10 |
9 |
Bit 8 |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
MOTOROLA |
|
OPERATING MODES AND ON-CHIP MEMORY |
M68HC11 E SERIES |
|||||||
|
4-6 |
|
|
|
|
|
|
|
|
TECHNICAL DATA |
|
Table 4-1 Register and Control Bit Assignments (Continued)
$1019 |
Bit 7 |
|
6 |
|
5 |
4 |
3 |
2 |
1 |
Bit 0 |
|
TOC2 (Low) |
|
$101A |
|
|
|
|
|
|
|
|
|
|
|
TOC3 (High) |
|
Bit 15 |
|
14 |
|
13 |
12 |
11 |
10 |
9 |
Bit 8 |
|
|
||
$101B |
|
|
|
|
|
|
|
|
|
|
|
TOC3 (Low) |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Bit 7 |
|
6 |
|
5 |
4 |
3 |
2 |
1 |
Bit 0 |
|
|
||
$101C |
|
|
|
|
|
|
|
|
|
|
|
TOC4 (High) |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Bit 15 |
|
14 |
|
13 |
12 |
11 |
10 |
9 |
Bit 8 |
|
|
||
$101D |
|
|
|
|
|
|
|
|
|
|
|
TOC4 (Low) |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Bit 7 |
|
6 |
|
5 |
4 |
3 |
2 |
1 |
Bit 0 |
|
|
||
$101E |
|
|
|
|
|
|
|
|
|
|
|
TI4/O5 (High) |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Bit 15 |
|
14 |
|
13 |
12 |
11 |
10 |
9 |
Bit 8 |
|
|
||
$101F |
|
|
|
|
|
|
|
|
|
|
|
TI4/O5 (Low) |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Bit 7 |
|
6 |
|
5 |
4 |
3 |
2 |
1 |
Bit 0 |
|
|
||
$1020 |
|
|
|
|
|
|
|
|
|
|
|
TCTL1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
OM2 |
|
OL2 |
|
OM3 |
OL3 |
OM4 |
OL4 |
OM5 |
OL5 |
|
|
||
$1021 |
|
|
|
|
|
|
|
|
|
|
|
TCTL2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
EDG4B |
|
EDG4A |
|
EDG1B |
EDG1A |
EDG2B |
EDG2A |
EDG3B |
EDG3A |
|
4 |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
$1022 |
OC1I |
|
OC2I |
|
OC3I |
OC4I |
I4/O5I |
IC1I |
IC2I |
IC3I |
|
TMSK1 |
|
|
|
|
|
||||||||||
$1023 |
|
|
|
|
|
|
|
|
|
|
|
TFLG1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
OC1F |
|
OC2F |
|
OC3F |
OC4F |
I4/O5F |
IC1F |
IC2F |
IC3F |
|
|
||
$1024 |
|
|
|
|
|
|
|
|
|
|
|
TMSK2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
TOI |
|
RTII |
|
PAOVI |
PAII |
0 |
0 |
PR1 |
PR0 |
|
|
||
$1025 |
|
|
|
|
|
|
|
|
|
|
|
TFLG2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
TOF |
|
RTIF |
|
PAOVF |
PAIF |
0 |
0 |
0 |
0 |
|
|
||
$1026 |
|
|
|
|
|
|
|
|
|
|
|
PACTL |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
DDRA7 |
|
PAEN |
|
PAMOD |
PEDGE |
DDRA3 |
I4/O5 |
RTR1 |
RTR0 |
|
|
||
$1027 |
|
|
|
|
|
|
|
|
|
|
|
PACNT |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Bit 7 |
|
6 |
|
5 |
4 |
3 |
2 |
1 |
Bit 0 |
|
|
||
$1028 |
|
|
|
|
|
|
|
|
|
|
|
SPCR |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
SPIE |
|
SPE |
|
DWOM |
MSTR |
CPOL |
CPHA |
SPR1 |
SPR0 |
|
|
||
$1029 |
|
|
|
|
|
|
|
|
|
|
|
SPSR |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
SPIF |
|
WCOL |
|
0 |
MODF |
0 |
0 |
0 |
0 |
|
|
||
$102A |
|
|
|
|
|
|
|
|
|
|
|
SPDR |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Bit 7 |
|
6 |
|
5 |
4 |
3 |
2 |
1 |
Bit 0 |
|
|
||
$102B |
|
|
|
|
|
|
|
|
|
|
|
BAUD |
|
|
|
|
|
|
|
|
|
|
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TCLR |
|
SCP21 |
|
SCP1 |
SCP0 |
RCKB |
SCR2 |
SCR1 |
SCR0 |
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||
$102C |
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SCCR1 |
|
R8 |
|
T8 |
|
0 |
M |
WAKE |
0 |
0 |
0 |
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$102D |
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SCCR2 |
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TIE |
|
TCIE |
|
RIE |
ILIE |
TE |
RE |
RWU |
SBK |
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$102E |
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SCSR |
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TDRE |
|
TC |
|
RDRF |
IDLE |
OR |
NF |
FE |
0 |
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||
$102F |
|
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SCDR |
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R7/T7 |
|
R6/T6 |
|
R5/T5 |
R4/T4 |
R3/T3 |
R2/T2 |
R1/T1 |
R0/T0 |
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||
$1030 |
|
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ADCTL |
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CCF |
|
0 |
|
SCAN |
MULT |
CD |
CC |
CB |
CA |
|
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||
$1031 |
|
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ADR1 |
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Bit 7 |
|
6 |
|
5 |
4 |
3 |
2 |
1 |
Bit 0 |
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||
$1032 |
|
|
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|
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|
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|
ADR2 |
|
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||
Bit 7 |
|
6 |
|
5 |
4 |
3 |
2 |
1 |
Bit 0 |
|
|
||
$1033 |
|
|
|
|
|
|
|
|
|
|
|
ADR3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Bit 7 |
|
6 |
|
5 |
4 |
3 |
2 |
1 |
Bit 0 |
|
|
||
|
|
|
|
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|
|
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|
M68HC11 E SERIES |
OPERATING MODES AND ON-CHIP MEMORY |
|
MOTOROLA |
|
|||||||||
TECHNICAL DATA |
|
|
|
|
|
|
|
|
4-7 |
|
|||
Table 4-1 Register and Control Bit Assignments (Continued)
|
$1034 |
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit 0 |
ADR4 |
|
$1035 |
|
|
|
|
|
|
|
|
BPROT |
|
0 |
0 |
0 |
PTCON |
BPRT3 |
BPRT2 |
BPRT1 |
BPRT0 |
||
|
$1036 |
|
|
|
|
|
|
|
|
EPROG2 |
|
|
|
|
|
|
|
|
|
||
|
MBE |
0 |
ELAT |
EXCOL |
EXROW |
T1 |
T0 |
PGM |
||
|
$1037 |
|
|
|
|
|
|
|
|
Reserved |
|
|
|
|
|
|
|
|
|
||
|
$1038 |
|
|
|
|
|
|
|
|
Reserved |
|
|
|
|
|
|
|
|
|
||
|
$1039 |
|
|
|
|
|
|
|
|
OPTION |
|
ADPU |
CSEL |
IRQE |
DLY |
CME |
0 |
CR1 |
CR0 |
||
|
$103A |
|
|
|
|
|
|
|
|
COPRST |
|
|
|
|
|
|
|
|
|
||
|
Bit 7 |
6 |
5 |
4 |
3 |
2 |
1 |
Bit 0 |
||
|
$103B |
|
|
|
|
|
|
|
|
PPROG |
|
|
|
|
|
|
|
|
|
||
|
ODD |
EVEN |
ELAT3 |
BYTE |
ROW |
ERASE |
EELAT |
EPGM |
||
|
$103C |
|
|
|
|
|
|
|
|
HPRIO |
4 |
RBOOT |
SMOD |
MDA |
IRVNE |
PSEL3 |
PSEL2 |
PSEL1 |
PSEL0 |
||
$103D |
|
|
|
|
|
|
|
|
INIT |
|
|
|
|
|
|
|
|
|
|||
RAM3 |
RAM2 |
RAM1 |
RAM0 |
REG3 |
REG2 |
REG1 |
REG0 |
|||
$103E |
|
|
|
|
|
|
|
|
TEST1 |
|
|
|
|
|
|
|
|
|
|||
TILOP |
0 |
OCCR |
CBYP |
DISR |
FCM |
FCOP |
TCON |
|||
|
$103F |
|
|
|
|
|
|
|
|
CONFIG |
|
EE34 |
EE24 |
EE14 |
EE04 |
NOSEC |
NOCOP |
ROMON |
EEON |
NOTES:
1.SCP2 adds 39 to SCI prescaler and is present only in MC68HC(7)11E20.
2.EPROG is present only in MC68HC711E20.
3.ELAT in PPROG is present only on MC68HC711E9 and MC68S711E9.
4.EEPROM mapping control bits EE[3:0] apply only to MC68HC811E2.
Hardware priority is built into RAM and I/O mapping. Registers have priority over RAM and RAM has priority over ROM. When a lower priority resource is mapped at the same location as a higher priority resource, a read/write of a location results in a read/ write of the higher priority resource only. For example, if both the register block and the RAM are mapped to the same location, only the register block will be accessed. If
RAM and ROM are located at the same position, RAM has priority.
The fully static RAM can be used to store instructions, variables, and temporary data.
The direct addressing mode can access RAM locations using a one-byte address operand, saving program memory space and execution time, depending on the application.
RAM contents can be preserved during periods of processor inactivity by two methods, both of which reduce power consumption.
In the software-based STOP mode, the clocks are stopped while VDD powers the MCU. Because power supply current is directly related to operating frequency in CMOS integrated circuits, only a very small amount of leakage exists when the clocks are stopped.
In the second method, the MODB/VSTBY pin can supply RAM power from a battery backup or from a second power supply. Figure 4-5 shows a typical standby voltage
MOTOROLA |
OPERATING MODES AND ON-CHIP MEMORY |
M68HC11 E SERIES |
4-8 |
|
TECHNICAL DATA |