Приложение
П.1. Листинг программ на VHDL
П.1.1 Реализация операции «Умножение»
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_arith.ALL;
PACKAGE Types IS
CONSTANT INT15 : INTEGER := 15;
CONSTANT INT31 : INTEGER := 31;
CONSTANT CONST016 : STD_LOGIC_VECTOR(INT15 DOWNTO 0) := X"0000";
CONSTANT CONST032 : SIGNED(INT31 DOWNTO 0) := X"00000000";
END Types;
USE WORK.Types.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_signed.ALL;
ENTITY mcu_op IS
PORT(
CLK, RST, LAB, SHIFT, SIGN, OUTHL, OE : in STD_ULOGIC;
DA, DB : in STD_LOGIC_VECTOR(INT15 DOWNTO 0);
DY : out STD_LOGIC_VECTOR(INT15 DOWNTO 0);
ZF : out STD_ULOGIC;
SF : out STD_ULOGIC
);
end mcu_op;
ARCHITECTURE COP OF mcu_op IS
COMPONENT OPNDRN -- О.К.
PORT ( a_in : IN STD_LOGIC;
a_out: OUT STD_LOGIC);
END COMPONENT;
COMPONENT TRi -- Z- буфер
PORT (A_in : IN STD_LOGIC;
OE : IN STD_LOGIC;
A_out : OUT STD_LOGIC);
END COMPONENT; -- signed (SHORT+1 DOWNTO 0);--
SIGNAL A, B, DP : STD_LOGIC_VECTOR(INT15 DOWNTO 0);--
SIGNAL S : SIGNED(INT15+1 DOWNTO 0);--
SIGNAL P : SIGNED(INT31 DOWNTO 0);--
SIGNAL ZFI : STD_LOGIC;
BEGIN
RG_A: PROCESS (CLK, RST)
BEGIN
IF RST = '1' THEN
A<=CONST016;
ELSIF CLK = '1' AND CLK'EVENT THEN
IF LAB = '1' THEN
A<= DA;
END IF;
END IF;
END PROCESS;
RG_B: PROCESS (CLK, RST)
BEGIN
IF RST = '1' THEN
B<=CONST016;
ELSIF CLK = '1' AND CLK'EVENT THEN
IF LAB = '1' THEN
B<= DB;
ELSIF SHIFT = '1' THEN
B<='0'& B(INT15 DOWNTO 1); -- SHIFT TO RIGHT
END IF;
END IF;
END PROCESS;
-- ADD|SUB
ADDER: S<=P(INT31) & P(INT31 DOWNTO INT15+1) - SIGNED(A) WHEN B(0) = '1' AND SIGN = '1' ELSE
P(INT31) & P(INT31 DOWNTO INT15+1) + SIGNED(A) WHEN B(0) = '1' ELSE
P(INT31) & P(INT31 DOWNTO INT15+1);
-- MULPY
RG_P: PROCESS (CLK, RST, P)
BEGIN
IF RST = '1' THEN
P<=CONST032;
ELSIF CLK = '1' AND CLK'EVENT THEN
IF LAB = '1' THEN
P<= CONST032;
ELSIF SHIFT = '1' THEN
P<=S & P(INT15 DOWNTO 1); -- SHIFT TO RIGHT
END IF;
END IF;
END PROCESS;
-- SELECTOR
DP <= STD_LOGIC_VECTOR(P(INT15 DOWNTO 0)) WHEN OUTHL = '1' ELSE
STD_LOGIC_VECTOR(P(INT31 DOWNTO 16));
SF <= P(INT15);
ZFI<='1' WHEN P(INT15 DOWNTO 0) = SIGNED(CONST016) ELSE '0';
OK_ZF: OPNDRN PORT MAP ( ZFI, ZF );
-- Generate Statement
TRIBus: FOR i IN 0 TO INT15 GENERATE
TRiBuffer: TRi PORT MAP (DP(i), OE, DY(i));
END GENERATE TRIBus;
end COP;
-- управляющий автомат для умножителя
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE IEEE.STD_LOGIC_arith.ALL;
--USE IEEE.STD_LOGIC_signed.ALL;
ENTITY mcu_ua IS
PORT(
CLK, RST, START : in STD_ULOGIC;
LAB, SHIFT, SIGN, RDY : out STD_ULOGIC
);
end mcu_ua;
ARCHITECTURE CUA OF mcu_ua IS
TYPE STATES IS (S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16,S17,FINISH);
SIGNAL ST : STATES;--
BEGIN
STATE: PROCESS (CLK, RST)
BEGIN
IF RST = '1' THEN
ST<=FINISH;
ELSIF CLK = '1' AND CLK'EVENT THEN
CASE ST IS
WHEN S1 => ST<= S2;
WHEN S2 => ST<= S3;
WHEN S3 => ST<= S4;
WHEN S4 => ST<= S5;
WHEN S5 => ST<= S6;
WHEN S6 => ST<= S7;
WHEN S7 => ST<= S8;
WHEN S8 => ST<= S9;
WHEN S9 => ST<= S10;
WHEN S10 => ST<= S11;
WHEN S11 => ST<= S12;
WHEN S12 => ST<= S13;
WHEN S13 => ST<= S14;
WHEN S14 => ST<= S15;
WHEN S15 => ST<= S16;
WHEN S16 => ST<= S17;
WHEN S17 => ST<= FINISH;
WHEN FINISH => IF START='1' THEN ST<= S1;
ELSE ST<=FINISH; END IF;
END CASE;
END IF;
END PROCESS;
LAB<='1' WHEN ST=S1 ELSE '0';
SHIFT<='0' WHEN ST=S1 OR ST=FINISH ELSE '1';
SIGN<='1' WHEN ST=S17 ELSE '0';
RDY<='1' WHEN ST=FINISH ELSE '0';
end CUA;