Лабораторная работа 2 / FastChip / laba2

// Netlist written October 26, 2006 2:59:52 AM MSD
// By FastChip Version 2.6.0 Build 030604-1706
// Netlist last modified October 26, 2006 2:59:39 AM MSD
netlist
module toplevel {
    %%props;
    unsourcedNets = "APPRST, SIN0, SIN1, FIQ, IRQ0, IRQ1, IRQ2, CTS, DSR, DCD, RI",
    doesNotOutdateBinding (
        MSSIU,
        Timer_0,
        Timer_1,
        UART_0,
        UART_1,
        ICU,
        Watchdog,
        DMA,
        Power,
        Scratchpad,
        Cache
    ),
    moduleTouchTimes (
        and1 = "1161813869786",
        and2 = "1161814066209",
        and3 = "1161814107068",
        and4 = "1161814645722",
        Cache = "0",
        Clocks = "0",
        DMA = "0",
        ICU = "0",
        invert = "1161815312311",
        MCU = "0",
        MSSIU = "0",
        or = "1161814203666",
        Power = "0",
        Scratchpad = "0",
        Timer_0 = "0",
        Timer_1 = "0",
        UART_0 = "0",
        UART_1 = "0",
        Watchdog = "0",
        X = "1161815137760",
        Y = "1161814278764"
    )
    %%end;
    net and1;
    net and2;
    net and3;
    net and4;
    net notX1;
    net notX2;
    net notX3;
    net notX4;
    net X1;
    net X2;
    net X3;
    net X4;
    net Y;
    wide4 @(and1:0,0) and1.AND_WIDE4_0_0 (.ci=vcc, .co=and1, .i={vcc,vcc,notX2,X3}, :initv="#b1000_0000_0000_0000", :widefunc="AND");
    wide4 @(and2:0,0) and2.AND_WIDE4_0_0 (.ci=vcc, .co=and2, .i={vcc,vcc,X1,X3}, :initv="#b1000_0000_0000_0000", :widefunc="AND");
    wide4 @(and3:0,0) and3.AND_WIDE4_0_0 (.ci=vcc, .co=and3, .i={vcc,X1,notX2,notX4}, :initv="#b1000_0000_0000_0000", :widefunc="AND");
    wide4 @(and4:0,0) and4.AND_WIDE4_0_0 (.ci=vcc, .co=and4, .i={vcc,notX1,notX3,X4}, :initv="#b1000_0000_0000_0000", :widefunc="AND");
    lut4 invert.inv_0 (.i={null,null,null,X4}, .o=notX4, :eq="~0");
    lut4 invert.inv_1 (.i={null,null,null,X3}, .o=notX3, :eq="~0");
    lut4 invert.inv_2 (.i={null,null,null,X2}, .o=notX2, :eq="~0");
    lut4 invert.inv_3 (.i={null,null,null,X1}, .o=notX1, :eq="~0");
    wide4 @(or:0,0) or.AND_WIDE4_0_0 (.ci=gnd, .co=Y, .i={and1,and2,and3,and4}, :initv="#b1111_1111_1111_1110", :widefunc="OR");
    tpad X.0 (.i=X4, .o=gnd, .oe=gnd, :busMinder="NONE", :hysteresis="true", :isClamped="false", :isInputLowPower="true");
    tpad X.1 (.i=X3, .o=gnd, .oe=gnd, :busMinder="NONE", :hysteresis="true", :isClamped="false", :isInputLowPower="true");
    tpad X.2 (.i=X2, .o=gnd, .oe=gnd, :busMinder="NONE", :hysteresis="true", :isClamped="false", :isInputLowPower="true");
    tpad X.3 (.i=X1, .o=gnd, .oe=gnd, :busMinder="NONE", :hysteresis="true", :isClamped="false", :isInputLowPower="true");
    tpad Y. (.o=Y, .oe=vcc, :drive="WEAK", :isOutputLowPower="true", :slewRate="SLOW");
}