Приложение а

Листинг микропрограммы операционного автомата приведен в Лист. 1 ниже.

Листинг 1 – Исходный код операционного автомата класса «И»

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity OA is

generic (n: natural:=8);

port (clk, reset: in std_logic;

D1: in std_logic_vector(2*n-1 downto 0);

D2: in std_logic_vector(n-1 downto 0);

f: in std_logic;

R: out std_logic_vector(2*n - 1 downto 0);

y:in std_logic_vector(26 downto 1);

x:out std_logic_vector(12 downto 0) );

end OA;

----------------------------------------------------------------------------------

architecture OA of OA is

signal a,c: std_logic_Vector(2*n - 1 downto 0);

signal b: std_logic_Vector(n downto 0);

signal cnt: std_logic_vector (2 downto 0);

signal Tgs, IRQ1, IRQ2: std_logic;

signal x2, x4, x6: std_logic;

begin

process (clk, reset) is

begin

if (reset = '1') then

A <= (others => '0');

B <= (others => '0');

C <= (others => '0');

Cnt <= "100";

IRQ1<= '0';

IRQ2<= '0';

elsif (clk'event and clk = '1')then

-- начало формирования микроопераций для А

if (y(1) = '1') then A<= D1;

elsif (y(5) = '1') then

A(2*n-1 downto n-1) <= IEEE.std_logic_signed."+"(A(2*n-1 downto n-1), (not B));

A(2*n-1 downto n-1) <= IEEE.std_logic_signed."+"(A(2*n-1 downto n-1), 1);

elsif (y(6) = '1') then

A(2*n-1 downto n-1) <= IEEE.std_logic_signed."+"(A(2*n-1 downto n-1), B);

elsif (y(12) = '1') then

A <= (A(2*n-2 downto 0)& '0');

elsif (y(13) = '1') then

A <= IEEE.std_logic_signed."+"(A,(not B));

A <= IEEE.std_logic_signed."+"(A,1);

elsif (y(14) = '1') then

A <= IEEE.std_logic_signed."+"(A,B);

elsif (y(19) = '1') then

A <= "000000000"& D1(n-1 downto 0);

elsif (y(21) = '1') then

A (n+1 downto 0) <= A(n downto 0) & '0';

end if;

-- начало формирования микроопераций для B

if (y(2) = '1') then

B(n downto 0) <= D2(n-1 downto 0) & '0';

elsif (y(4) = '1') then

B(n downto 0) <= B(n) & B(n downto 1);

elsif (y(20) = '1') then

B(n-1 downto 0) <= D2;

elsif (y(24) = '1') then

B(n downto 0) <= C(1 downto 0)& B(n downto 2);

end if;

-- начало формирования микроопераций для C

if (y(7) = '1') then

C <= (others => '0');

elsif (y(9) = '1') then

C(n-1 downto 0) <= C (n-2 downto 0) &'1';

elsif (y(10) = '1') then

C(n-1 downto 0) <= C (n-2 downto 0) &'0';

elsif (y(15) = '1') then

C(n-1 downto 0) <= IEEE.std_logic_unsigned."+"(C(n-1 downto 0),1);

elsif (y(22) = '1') then

C(n+1 downto 0) <= IEEE.std_logic_unsigned."+"(C(n+1 downto 0),A(n+1 downto 0));

elsif (y(23) = '1') then

C(n+1 downto 0) <= IEEE.std_logic_unsigned."+"(C(n+1 downto 0),(not A(n+1 downto 0)));

C(n+1 downto 0) <= IEEE.std_logic_unsigned."+"(C(n+1 downto 0),1);

elsif (y(25) = '1') then

C(n+1 downto 0) <= C(n+1) & C(n+1)& C(n+1 downto 2);

end if;

-- начало формирования микроопераций для TgS

if (y(3) = '1') then

TgS <= A(2*n -1);

end if;

-- начало формирования микроопераций для CnT

if (y(8) = '1') then

Cnt <= "100";

elsif (y(11) = '1') then

Cnt <= Cnt - 1;

end if;

if (y(17) = '1') then

IRQ1 <= '1';

elsif (y(18) = '1') then

IRQ2 <= '1';

end if;

end if;

end process;

-- запись результата в реигстр

R <= "000000000"& C(n-1 downto 0) when y(16) = '1' else

C(n-1 downto 0)& B(n-1 downto 0) when y(26) = '1' else (others => 'Z');

x2 <= (A(2*n-1)and (not B(n))) or ((not A(2*n-1)) and B(n));

x4 <= (A(2*n-1)and (not TgS)) or ((not A(2*n-1)) and TgS);

x6 <= (B(n)and (not TgS)) or ((not B(n)) and TgS);

X(0) <= F;

X(1) <= '1' when B = "00000000" else '0';

X(2) <= '1' when x2 = '1' else '0';

X(3) <= '1' when CnT = 0 else '0';

X(4) <= '1' when x4 = '1' else '0';

X(5) <= '1' when B(n) ='1' else '0';

X(6) <= '1' when x6 = '1' else '0';

X(7) <= '1' when TgS = '1' else '0';

X(8) <= '1' when A = "0000000000000000" else '1';

X(9) <= B(1) and (C(n+1) xor B(0));

X(10) <= ((not C(n+1)) and B(1) and (not B(0))) or (C(n+1) and (not B(1)) and B(0));

X(11) <= B(1) and (C(n+1)xor B(0));

X(12) <= C(n+1);

end architecture;

Листинг микропрограммы управляющего автомата приведен в Лист. 2 ниже.

Листинг 2 – Исходный код управляющего автомата Мили

library ieee;

use ieee.std_logic_1164.all;

use std.textio.all;

entity FSM_Mealy is

port(clk, reset:in std_logic;

x: in std_logic_vector(12 downto 0);

y: out std_logic_vector(26 downto 1));

end entity;

architecture FSM_Mealy of FSM_Mealy is

procedure ControlUnitDEBUG( OutputFileName: in string; src: in string) is

file outFile: text open append_mode is OutputFileName;

variable buff:line;

begin

write(buff, "Управляющий автомат: состояние ");

write(buff, " ");

write(buff, src);

writeline(outFile, buff);

FILE_CLOSE(outFile);

end procedure;

type TState is (S0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15, s16);

signal curr_state, state: TState;

begin

-- двух процессная модель

process (state, x) is

begin

case state is

when S0 => y(26 downto 1) <= (others => '0');

if (x(0) = '0') then

curr_state <= S1;

-- y(26 downto 1) <= (others => '0');

Y(19) <= '1';

Y(20) <= '1';

Y(7) <= '1';

Y(8) <= '1';

ControlUnitDEBUG("c:\debug.txt", "Current State S0 Next state S1");

elsif (x(0) = '1') then

Y(1) <= '1';

Y(2) <= '1';

curr_state <= S2;

ControlUnitDEBUG("c:\debug.txt", "Current State S0 Next state S2");

end if;

when S1=> y(26 downto 1) <= (others => '0');

if (x(9) = '0' and x(10) = '1') then

curr_state <= S3;

Y(21) <= '1';

ControlUnitDEBUG("c:\debug.txt", "Current State S1 Next state S3");

elsif (x(9) = '1') then

Y(22) <= '1';

curr_state <= S4;

ControlUnitDEBUG("c:\debug.txt", "Current State S1 Next state S3");

elsif (x(9) = '0' and x(10) = '0' and x(11) = '1') then

Y(23) <= '1';

curr_state <= S4;

--ControlUnitDEBUG("c:\debug.txt", "S0");

elsif (x(9) = '0' and x(10) = '0' and x(11) = '0') then

curr_state <= S4;

end if;

when S2 => y(26 downto 1) <= (others => '0');

if (x(1) = '0') then

curr_state <= s7;

y(4) <= '1';

y(3) <= '1';

else

curr_state <= S0;

y(17) <= '1';

end if;

when S3 => y(26 downto 1) <= (others => '0');

curr_state <= S4;

y(22) <= '1';

when S4 => y(26 downto 1) <= (others => '0');

curr_state <= S5;

y(24) <= '1';

y(25) <= '1';

y(11) <= '1';

when S5 => y(26 downto 1) <= (others => '0');

if (x(3) = '0') then

curr_state <= S1;

--y(25) <= '1';

elsif (x(3) = '1' and x(12) = '1') then

curr_state <= s6;

y(22) <= '1';

elsif (x(3) = '1' and x(12) = '0') then

curr_state <= s6;

end if;

when S6 => y(26 downto 1) <= (others => '0');

curr_state <= S0;

y(26) <= '1';

when S7 => y(26 downto 1) <= (others => '0');

if (x(2) = '0') then

curr_state <= S8;

y(5) <= '1';

else

curr_state <= S9;

y(6) <= '1';

end if;

when S8 => y(26 downto 1) <= (others => '0');

if (x(2) = '1') then

y(18) <= '1';

curr_state <= S0;

else

y(7) <= '1';

y(8) <= '1';

curr_state <= S10;

end if;

when S9 => y(26 downto 1) <= (others => '0');

if (x(2) = '1') then

y(18) <= '1';

curr_state <= S0;

else

y(7) <= '1';

y(8) <= '1';

curr_state <= S10;

end if;

when S10 => y(26 downto 1) <= (others => '0');

if (x(2) = '0') then

curr_state <= S11;

y(9) <= '1';

else

curr_state <= S11;

y(10) <= '1';

end if;

when S11 => y(26 downto 1) <= (others => '0');

y(11) <= '1';

curr_state <= S12;

when S12 => y(26 downto 1) <= (others => '0');

if (x(2) = '0' and x(3) = '0') then

y(12) <= '1';

curr_state <= S13;

elsif (x(2) = '1' and x(3) = '0') then

y(12) <= '1';

curr_state <= S14;

elsif (x(4) = '1' and x(5) = '1') then

y(13) <= '1';

curr_state <= S15;

elsif (x(4) = '1' and x(5) = '0') then

y(14) <= '1';

curr_state <= S15;

end if;

when S13 => y(26 downto 1) <= (others => '0');

y(13) <= '1';

curr_state <= S10;

when S14 => y(26 downto 1) <= (others => '0');

y(14) <= '1';

curr_state <= S10;

when S15 => y(26 downto 1) <= (others => '0');

if ((x(6) = '1' and x(7) = '1' and x(8) = '1')

or (x(6) = '0' and x(7) = '0' )

or (x(6) = '0' and x(7) = '1' and x(8) = '0' ))then

curr_state <= S0;

elsif (x(6) = '1' and x(7) = '0') then

curr_state <= S16;

y(15) <= '1';

elsif (x(6) = '1' and x(7) = '1' and x(8) = '0' ) then

curr_state <= S16;

y(15) <= '1';

elsif (x(6) = '0' and x(7) = '1' and x(8) = '1' ) then

curr_state <= S16;

y(15) <= '1';

end if;

when S16 => y(26 downto 1) <= (others => '0');

curr_state <= S0;

y(16)<= '1';

end case;

end process;

process (clk, reset) is

begin

if (reset = '1') then

State <= S0;

elsif (clk'event and clk = '0') then

state <= curr_state;

end if;

end process;

end;