
- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Disclaimer
- •Pin Descriptions
- •Port C (PC5..PC0)
- •PC6/RESET
- •Port D (PD7..PD0)
- •RESET
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Register Description for I/O Ports
- •External Interrupts
- •8-bit Timer/Counter0
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Operation
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •16-bit Timer/Counter1
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Pin Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •8-bit Timer/Counter2 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •SS Pin Functionality
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Overview
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bits
- •Sending Frames with 9 Data Bits
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Write Access
- •Read Access
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •SCL and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog Comparator Multiplexed Input
- •Features
- •Starting a Conversion
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0
- •ADLAR = 1
- •Boot Loader Features
- •Application Section
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Page Size
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Power-save Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Erratas
- •Changes from Rev. 2486N-09/04 to Rev. 2486O-10/04
- •Changes from Rev. 2486M-12/03 to Rev. 2486N-09/04
- •Changes from Rev. 2486L-10/03 to Rev. 2486M-12/03
- •Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03
- •Changes from Rev. 2486J-02/03 to Rev. 2486K-08/03
- •Changes from Rev. 2486I-12/02 to Rev. 2486J-02/03
- •Changes from Rev. 2486H-09/02 to Rev. 2486I-12/02
- •Changes from Rev. 2486G-09/02 to Rev. 2486H-09/02
- •Changes from Rev. 2486F-07/02 to Rev. 2486G-09/02
- •Changes from Rev. 2486E-06/02 to Rev. 2486F-07/02
- •Changes from Rev. 2486D-03/02 to Rev. 2486E-06/02
- •Changes from Rev. 2486C-03/02 to Rev. 2486D-03/02
- •Changes from Rev. 2486B-12/01 to Rev. 2486C-03/02
- •Table of Contents

Table 86. Lock Bit Protection Modes(2) (Continued)
Memory Lock Bits |
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Protection Type |
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1 |
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1 |
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1 |
No restrictions for SPM or LPM accessing the Boot Loader |
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section. |
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2 |
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1 |
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0 |
SPM is not allowed to write to the Boot Loader section. |
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SPM is not allowed to write to the Boot Loader section, |
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and LPM executing from the Application section is not |
3 |
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0 |
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0 |
allowed to read from the Boot Loader section. If Interrupt |
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Vectors are placed in the Application section, interrupts |
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are disabled while executing from the Boot Loader section. |
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LPM executing from the Application section is not allowed |
4 |
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0 |
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1 |
to read from the Boot Loader section. If Interrupt Vectors |
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are placed in the Application section, interrupts are |
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disabled while executing from the Boot Loader section. |
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Notes: 1. Program the Fuse Bits before programming the Lock Bits. |
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2. “1” means unprogrammed, “0” means programmed |
Fuse Bits |
The ATmega8 has two fuse bytes. Table 87 and Table 88 describe briefly the functional- |
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ity of all the fuses and how they are mapped into the fuse bytes. Note that the fuses are |
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read as logical zero, “0”, if they are programmed. |
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Table 87. Fuse High Byte |
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Fuse High |
Bit |
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Byte |
No. |
Description |
Default Value |
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RSTDISBL(4) |
7 |
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1 |
(unprogrammed, PC6 is |
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Select if PC6 is I/O pin or RESET pin |
RESET-pin) |
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WDTON |
6 |
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1 |
(unprogrammed, WDT |
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WDT always on |
enabled by WDTCR) |
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SPIEN(1) |
5 |
Enable Serial Program and Data |
0 |
(programmed, SPI prog. |
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Downloading |
enabled) |
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CKOPT(2) |
4 |
Oscillator options |
1 |
(unprogrammed) |
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EESAVE |
3 |
EEPROM memory is preserved |
1 |
(unprogrammed, |
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through the Chip Erase |
EEPROM not preserved) |
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BOOTSZ1 |
2 |
Select Boot Size (see Table 82 for |
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(programmed)(3) |
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details) |
0 |
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BOOTSZ0 |
1 |
Select Boot Size (see Table 82 for |
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(programmed)(3) |
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details) |
0 |
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BOOTRST |
0 |
Select Reset Vector |
1 |
(unprogrammed) |
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Notes: 1. The SPIEN Fuse is not accessible in Serial Programming mode. |
2.The CKOPT Fuse functionality depends on the setting of the CKSEL bits, see “Clock Sources” on page 24 for details.
3.The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 82 on page 217.
4.When programming the RSTDISBL Fuse Parallel Programming has to be used to change fuses or perform further programming.
220 ATmega8(L)
2486O–AVR–10/04

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ATmega8(L) |
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Table 88. Fuse Low Byte |
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Fuse Low |
Bit |
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Byte |
No. |
Description |
Default Value |
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BODLEVEL |
7 |
Brown out detector trigger level |
1 |
(unprogrammed) |
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BODEN |
6 |
Brown out detector enable |
1 |
(unprogrammed, BOD disabled) |
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SUT1 |
5 |
Select start-up time |
1 |
(unprogrammed)(1) |
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SUT0 |
4 |
Select start-up time |
0 |
(programmed)(1) |
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CKSEL3 |
3 |
Select Clock source |
0 |
(programmed)(2) |
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CKSEL2 |
2 |
Select Clock source |
0 |
(programmed)(2) |
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CKSEL1 |
1 |
Select Clock source |
0 |
(programmed)(2) |
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CKSEL0 |
0 |
Select Clock source |
1 |
(unprogrammed)(2) |
Notes: 1. The default value of SUT1..0 results in maximum start-up time. SeeTable 10 on page 28 for details.
2.The default setting of CKSEL3..0 results in internal RC Oscillator @ 1MHz. See Table 2 on page 24 for details.
The status of the Fuse Bits is not affected by Chip Erase. Note that the Fuse Bits are locked if lock bit1 (LB1) is programmed. Program the Fuse Bits before programming the Lock Bits.
Latching of Fuses |
The fuse values are latched when the device enters Programming mode and changes of |
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the fuse values will have no effect until the part leaves Programming mode. This does |
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not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses |
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are also latched on Power-up in Normal mode. |
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2486O–AVR–10/04