		ATmega128
Table of Contents	Features................................................................................................	1
	Pin Configurations...............................................................................	2
	Overview...............................................................................................	2
	Block Diagram ......................................................................................................	3
	ATmega103 and ATmega128 Compatibility .........................................................	4
	Pin Descriptions....................................................................................................	5
	About Code Examples.........................................................................	7
	AVR CPU Core .....................................................................................	8
	Introduction ...........................................................................................................	8
	Architectural Overview..........................................................................................	8
	ALU – Arithmetic Logic Unit..................................................................................	9
	Status Register .....................................................................................................	9
	General Purpose Register File ...........................................................................	10
	Stack Pointer ......................................................................................................	12
	Instruction Execution Timing...............................................................................	13
	Reset and Interrupt Handling..............................................................................	13
	AVR ATmega128 Memories ..............................................................	16
	In-System Reprogrammable Flash Program Memory ........................................	16
	SRAM Data Memory...........................................................................................	17
	EEPROM Data Memory......................................................................................	19
	I/O Memory .........................................................................................................	24
	External Memory Interface..................................................................................	24
	System Clock and Clock Options ....................................................	34
	Clock Systems and their Distribution ..................................................................	34
	Clock Sources.....................................................................................................	35
	Default Clock Source ..........................................................................................	35
	Crystal Oscillator.................................................................................................	36
	Low-frequency Crystal Oscillator ........................................................................	37
	External RC Oscillator ........................................................................................	38
	Calibrated Internal RC Oscillator ........................................................................	39
	External Clock.....................................................................................................	40
	Timer/Counter Oscillator.....................................................................................	41
	Power Management and Sleep Modes.............................................	42
	Idle Mode ............................................................................................................	43
	ADC Noise Reduction Mode...............................................................................	43
	Power-down Mode..............................................................................................	43
	Power-save Mode...............................................................................................	43
	Standby Mode.....................................................................................................	44
	Extended Standby Mode ....................................................................................	44
		i
2467M–AVR–11/04

Minimizing Power Consumption .........................................................................	45
System Control and Reset ................................................................	47
Internal Voltage Reference .................................................................................	52
Watchdog Timer .................................................................................................	52
Timed Sequences for Changing the Configuration of the Watchdog Timer .......	55
Interrupts ............................................................................................	57
Interrupt Vectors in ATmega128.........................................................................	57
I/O Ports..............................................................................................	63
Introduction .........................................................................................................	63
Ports as General Digital I/O ................................................................................	64
Alternate Port Functions .....................................................................................	68
Register Description for I/O Ports .......................................................................	84
External Interrupts.............................................................................	87
8-bit Timer/Counter0 with PWM and Asynchronous Operation ....	90
Overview.............................................................................................................	90
Timer/Counter Clock Sources.............................................................................	91
Counter Unit........................................................................................................	91
Output Compare Unit..........................................................................................	92
Compare Match Output Unit ...............................................................................	94
Modes of Operation ............................................................................................	95
Timer/Counter Timing Diagrams.........................................................................	99
8-bit Timer/Counter Register Description .........................................................	101
Asynchronous Operation of the Timer/Counter ................................................	104
Timer/Counter Prescaler...................................................................................	107
16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3).......	109
Overview...........................................................................................................	109
Accessing 16-bit Registers ...............................................................................	112
Timer/Counter Clock Sources...........................................................................	115
Counter Unit......................................................................................................	115
Input Capture Unit.............................................................................................	116
Output Compare Units ......................................................................................	118
Compare Match Output Unit .............................................................................	120
Modes of Operation ..........................................................................................	121
Timer/Counter Timing Diagrams.......................................................................	128
16-bit Timer/Counter Register Description .......................................................	131

Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers ...

142

8-bit Timer/Counter2 with PWM......................................................

144

ii ATmega128

2467M–AVR–11/04

ATmega128

Overview...........................................................................................................	144
Timer/Counter Clock Sources...........................................................................	145
Counter Unit......................................................................................................	145
Output Compare Unit........................................................................................	146
Compare Match Output Unit .............................................................................	148
Modes of Operation ..........................................................................................	149
Timer/Counter Timing Diagrams.......................................................................	154
8-bit Timer/Counter Register Description .....................................	156
Output Compare Modulator (OCM1C2)..........................................	160
Overview...........................................................................................................	160
Description........................................................................................................	160
Serial Peripheral Interface – SPI.....................................................	162
SS Pin Functionality..........................................................................................	166
Data Modes ......................................................................................................	169
USART ..............................................................................................	170
Overview...........................................................................................................	170
Clock Generation ..............................................................................................	172
Frame Formats .................................................................................................	175
USART Initialization..........................................................................................	176
Data Transmission – The USART Transmitter .................................................	177
Data Reception – The USART Receiver ..........................................................	180
Asynchronous Data Reception .........................................................................	184
Multi-processor Communication Mode .............................................................	187
USART Register Description ............................................................................	189
Examples of Baud Rate Setting........................................................................	194
Two-wire Serial Interface ................................................................	198
Features............................................................................................................	198
Two-wire Serial Interface Bus Definition...........................................................	198
Data Transfer and Frame Format .....................................................................	199
Multi-master Bus Systems, Arbitration and Synchronization ............................	201
Overview of the TWI Module ............................................................................	204
TWI Register Description..................................................................................	206
Using the TWI ...................................................................................................	209
Transmission Modes.........................................................................................	213
Multi-master Systems and Arbitration...............................................................	226
Analog Comparator .........................................................................	228
Analog Comparator Multiplexed Input ..............................................................	229
Analog to Digital Converter ............................................................	231

iii

2467M–AVR–11/04

Features............................................................................................................	231
Operation ..........................................................................................................	233
Starting a Conversion .......................................................................................	233
Prescaling and Conversion Timing ...................................................................	234
Changing Channel or Reference Selection ......................................................	236
ADC Noise Canceler.........................................................................................	237
ADC Conversion Result....................................................................................	242
JTAG Interface and On-chip Debug System .................................	248
Features............................................................................................................	248
Overview...........................................................................................................	248
Test Access Port – TAP....................................................................................	248
TAP Controller ..................................................................................................	250
Using the Boundary-scan Chain .......................................................................	251
Using the On-chip Debug System ....................................................................	251
On-chip Debug Specific JTAG Instructions ......................................................	252
On-chip Debug Related Register in I/O Memory ..............................................	253
Using the JTAG Programming Capabilities ......................................................	253
Bibliography ......................................................................................................	253
IEEE 1149.1 (JTAG) Boundary-scan................................................................	254
Features............................................................................................................	254
System Overview..............................................................................................	254
Data Registers ..................................................................................................	254
Boundary-scan Specific JTAG Instructions ......................................................	256
Boundary-scan Related Register in I/O Memory ..............................................	257
Boundary-scan Chain .......................................................................................	258
ATmega128 Boundary-scan Order...................................................................	268
Boundary-scan Description Language Files .....................................................	274
Boot Loader Support – Read-While-Write Self-Programming.....	275
Boot Loader Features .......................................................................................	275
Application and Boot Loader Flash Sections ....................................................	275
Read-While-Write and No Read-While-Write Flash Sections...........................	275
Boot Loader Lock Bits.......................................................................................	277
Entering the Boot Loader Program ...................................................................	278
Addressing the Flash During Self-Programming ..............................................	280
Self-Programming the Flash .............................................................................	281
Memory Programming.....................................................................	288
Program and Data Memory Lock Bits...............................................................	288
Fuse Bits...........................................................................................................	289
Signature Bytes ................................................................................................	291
Calibration Byte ................................................................................................	291
Parallel Programming Parameters, Pin Mapping, and Commands ..................	292
Parallel Programming .......................................................................................	294
Serial Downloading...........................................................................................	303

iv ATmega128

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	ATmega128
SPI Serial Programming Pin Mapping ..............................................................	303
Programming Via the JTAG Interface...............................................................	308
Electrical Characteristics................................................................	321
Absolute Maximum Ratings*.............................................................................	321
DC Characteristics............................................................................................	321
External Clock Drive Waveforms ......................................................................	322
External Clock Drive .........................................................................................	323
Two-wire Serial Interface Characteristics .........................................................	324
SPI Timing Characteristics ...............................................................................	325
ADC Characteristics .........................................................................................	327
External Data Memory Timing ..........................................................................	330
ATmega128 Typical Characteristics ..............................................	335
Register Summary ...........................................................................	364
Instruction Set Summary ................................................................	367
Ordering Information.......................................................................	370
Packaging Information ....................................................................	371
64A ...................................................................................................................	371
64M1.................................................................................................................	372
Errata ................................................................................................	373
ATmega128 Rev. I............................................................................................	373
ATmega128 Rev. H ..........................................................................................	374
ATmega128 Rev. G ..........................................................................................	375
ATmega128 Rev. F...........................................................................................	377
Datasheet Revision History ............................................................	379
Changes from Rev. 2467L-05/04 to Rev.
2467M-11/04.....................................................................................................	379
Changes from Rev. 2467K-03/04 to Rev.
2467L-05/04......................................................................................................	379
Changes from Rev. 2467J-12/03 to Rev.
2467K-03/04 .....................................................................................................	379
Changes from Rev. 2467I-09/03 to Rev.
2467J-12/03......................................................................................................	379
Changes from Rev. 2467H-02/03 to Rev. 2467I-09/03 ....................................	379
Changes from Rev. 2467G-09/02 to Rev. 2467H-02/03...................................	380
Changes from Rev. 2467F-09/02 to Rev. 2467G-09/02 ...................................	380
Changes from Rev. 2467E-04/02 to Rev. 2467F-09/02 ...................................	380
Changes from Rev. 2467D-03/02 to Rev. 2467E-04/02 ...................................	381
Changes from Rev. 2467C-02/02 to Rev. 2467D-03/02...................................	381
Changes from Rev. 2467B-09/01 to Rev. 2467C-02/02 ...................................	382
	v

2467M–AVR–11/04



.................................................................................Table of Contents				i

vi ATmega128

2467M–AVR–11/04

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