- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE7..PE0)
- •Port F (PF7..PF0)
- •Port G (PG4..PG0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •ATmega103 Compatibility
- •Address Latch Requirements
- •Pull-up and Bus-keeper
- •Timing
- •XMEM Register Description
- •Using all Locations of External Memory Smaller than 64 KB
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Alternate Functions of Port F
- •Alternate Functions of Port G
- •Register Description for I/O Ports
- •External Interrupts
- •8-bit Timer/Counter0 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Pin Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter2 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Overview
- •Description
- •Timing Example
- •SS Pin Functionality
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Dual USART
- •Overview
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •Scl and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog to Digital Converter
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0:
- •ADLAR = 1:
- •Features
- •Overview
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Device Identification Register
- •Version
- •Part Number
- •Manufacturer ID
- •Reset Register
- •Boundary-scan Chain
- •EXTEST; $0
- •IDCODE; $1
- •SAMPLE_PRELOAD; $2
- •AVR_RESET; $C
- •BYPASS; $F
- •Boundary-scan Chain
- •Scanning the Digital Port Pins
- •Scanning the RESET Pin
- •Scanning the Clock Pins
- •Scanning the ADC
- •Boot Loader Features
- •Application Section
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •PROG_COMMANDS ($5)
- •PROG_PAGELOAD ($6)
- •PROG_PAGEREAD ($7)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Programming Command Register
- •Virtual Flash Page Read Register
- •Programming Algorithm
- •Entering Programming Mode
- •Leaving Programming Mode
- •Performing Chip Erase
- •Programming the Flash
- •Reading the Flash
- •Programming the EEPROM
- •Reading the EEPROM
- •Programming the Fuses
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics
- •External Data Memory Timing
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Power-save Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Current Consumption in Reset and Reset Pulse width
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega128 Rev. I
- •ATmega128 Rev. H
- •ATmega128 Rev. G
- •ATmega128 Rev. F
- •Changes from Rev. 2467L-05/04 to Rev. 2467M-11/04
- •Changes from Rev. 2467K-03/04 to Rev. 2467L-05/04
- •Changes from Rev. 2467J-12/03 to Rev. 2467K-03/04
- •Changes from Rev. 2467I-09/03 to Rev. 2467J-12/03
- •Changes from Rev. 2467H-02/03 to Rev. 2467I-09/03
- •Changes from Rev. 2467G-09/02 to Rev. 2467H-02/03
- •Changes from Rev. 2467F-09/02 to Rev. 2467G-09/02
- •Changes from Rev. 2467E-04/02 to Rev. 2467F-09/02
- •Changes from Rev. 2467D-03/02 to Rev. 2467E-04/02
- •Changes from Rev. 2467C-02/02 to Rev. 2467D-03/02
- •Changes from Rev. 2467B-09/01 to Rev. 2467C-02/02
- •Table of Contents
Current Consumption in Reset and Reset Pulse width
Figure 209. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up)
RESET SUPPLY CURRENT vs. VCC
EXCLUDING CURRENT THROUGH THE RESET PULLUP
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4.5 |
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4 |
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5.5 V |
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3.5 |
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5.0 V |
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3 |
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4.5 V |
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4.0 V |
(mA) |
2.5 |
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3.6 V |
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3.3 V |
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CC |
2 |
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3.0 V |
I |
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2.7 V |
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1.5 |
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1 |
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0.5 |
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0 |
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0 |
0.1 |
0.2 |
0.3 |
0.4 |
0.5 |
0.6 |
0.7 |
0.8 |
0.9 |
1 |
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Frequency (MHz) |
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Figure 210. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through The
Reset Pull-up)
RESET SUPPLY CURRENT vs. VCC
1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP
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40 |
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35 |
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5.5 V |
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30 |
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5.0 V |
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25 |
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4.5 V |
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(mA) |
20 |
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4.0 V |
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3.6 V |
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CC |
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3.3 V |
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I |
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15 |
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3.0 V |
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2.7 V |
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10 |
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5 |
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0 |
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0 |
2 |
4 |
6 |
8 |
10 |
12 |
14 |
16 |
18 |
20 |
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Frequency (MHz) |
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360 ATmega128 
2467M–AVR–11/04
ATmega128
Figure 211. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5.0V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
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VCC = 5V |
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120 |
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-40 °C |
25 °C |
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100 |
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85 °C |
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80 |
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(uA) |
60 |
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RESET |
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I |
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40 |
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20 |
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0 |
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0 |
1 |
2 |
3 |
4 |
5 |
6 |
VRESET (V)
Figure 212. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
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VCC = 2.7V |
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60 |
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-40 °C |
25 °C |
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50 |
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85 °C |
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40 |
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(uA) |
30 |
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RESET |
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I |
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20 |
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10 |
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0 |
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0 |
0.5 |
1 |
1.5 |
2 |
2.5 |
3 |
VRESET (V)
361
2467M–AVR–11/04
Figure 213. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as ‘1’)
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIH, RESET PIN READ AS '1'
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2.5 |
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2 |
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-40 °C |
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(V) |
1.5 |
25 °C |
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Threshold |
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85 °C |
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1 |
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0.5 |
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0 |
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2.5 |
3 |
3.5 |
4 |
4.5 |
5 |
5.5 |
VCC (V)
Figure 214. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as ‘0’)
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0'
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2.5 |
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-40 ˚C |
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25 ˚C |
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85 ˚C |
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2 |
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Threshold (V) |
1.5 |
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1 |
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0.5 |
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0 |
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2.5 |
3 |
3.5 |
4 |
4.5 |
5 |
5.5 |
VCC (V)
362 ATmega128
2467M–AVR–11/04
ATmega128
Figure 215. Reset Input Pin Hysteresis vs. VCC
RESET INPUT PIN HYSTERESIS vs. VCC
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0.5 |
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0.45 |
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0.4 |
-40 ˚C |
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(mV) |
0.35 |
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0.3 |
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Hysteresis |
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0.25 |
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0.2 |
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Input |
25 ˚C |
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0.15 |
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0.1 |
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0.05 |
85 ˚C |
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0 |
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2.5 |
3 |
3.5 |
4 |
4.5 |
5 |
5.5 |
VCC (V)
Figure 216. Reset Pulse width vs. VCC (External Clock, 1 MHz)
RESET PULSE WIDTH vs. VCC
External Clock, 1 MHz
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1.2 |
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1 |
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(us) |
0.8 |
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Pulsewidth |
0.6 |
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85 |
°C |
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0.4 |
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25 |
°C |
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-40 |
°C |
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0.2 |
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0 |
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2.5 |
3 |
3.5 |
4 |
4.5 |
5 |
5.5 |
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VCC (V)
363
2467M–AVR–11/04