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Московский государственный технический университет им. H.Э.Баумана

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Микропроцессорные устройства систем управления

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08 семестр / Разное / Скамко / inform / ATmega128.pdf

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ATmega128

ADC Characteristics

Table 135. ADC Characteristics, Single Ended Channels

Symbol	Parameter	Condition	Min(1)	Typ(1)	Max(1)	Units
	Resolution	Single Ended Conversion			10	Bits

		Single Ended Conversion
		VREF = 4V, VCC = 4V		1.5		LSB
		ADC clock = 200 kHz

		Single Ended Conversion
		VREF = 4V, VCC = 4V		3.25		LSB
	Absolute Accuracy	ADC clock = 1 MHz

		Single Ended Conversion
	(Including INL, DNL, Quantization Error, Gain	Single Ended Conversion
	(Including INL, DNL, Quantization Error, Gain	VREF = 4V, VCC = 4V
	and Offset Error)	VREF = 4V, VCC = 4V		1.5		LSB
	and Offset Error)	ADC clock = 200 kHz		1.5		LSB
		ADC clock = 200 kHz
		Noise Reduction mode

		Single Ended Conversion
		VREF = 4V, VCC = 4V		3.75		LSB
		ADC clock = 1 MHz		3.75		LSB
		ADC clock = 1 MHz
		Noise Reduction mode

		Single Ended Conversion
	Integral Non-Linearity (INL)	VREF = 4V, VCC = 4V		0.75		LSB
		ADC clock = 200 kHz

		Single Ended Conversion
	Differential Non-Linearity (DNL)	VREF = 4V, VCC = 4V		0.5		LSB
		ADC clock = 200 kHz

		Single Ended Conversion
	Gain Error	VREF = 4V, VCC = 4V		1		LSB
		ADC clock = 200 kHz

		Single Ended Conversion
	Offset error	VREF = 4V, VCC = 4V		1		LSB
		ADC clock = 200 kHz

	Clock Frequency		50		1000	kHz

	Conversion Time		13		260	µs

AVCC	Analog Supply Voltage		VCC - 0.3(2)		VCC + 0.3(3)	V
VREF	Reference Voltage		2.0		AVCC	V
VIN	Input Voltage		GND		VREF	V
	Input Bandwidth				38.5	kHz

VINT	Internal Voltage Reference		2.3	2.56	2.7	V
RREF	Reference Input Resistance			32		kΩ
RAIN	Analog Input Resistance		55	100		MΩ

Notes: 1. Values are guidelines only.

2.Minimum for AVCC is 2.7V.

3.Maximum for AVCC is 5.5V

327

2467M–AVR–11/04

Table 136. ADC Characteristics, Differential Channels

Symbol	Parameter	Condition		Min(1)	Typ(1)	Max(1)	Units
		Gain =	1x			10	Bits

	Resolution	Gain =	10x			10	Bits

		Gain = 200x				10	Bits

		Gain = 1x
		VREF = 4V, VCC = 5V			17		LSB
		ADC clock = 50 - 200 kHz

		Gain = 10x
	Absolute Accuracy	VREF = 4V, VCC = 5V			17		LSB
		ADC clock = 50 - 200 kHz

		Gain = 200x
		VREF = 4V, VCC = 5V			7		LSB
		ADC clock = 50 - 200 kHz

		Gain = 1x
		VREF = 4V, VCC = 5V			1.5		LSB
		ADC clock = 50 - 200 kHz
	Integral Non-Linearity (INL)
	Integral Non-Linearity (INL)	Gain = 10x
	(Accuracy after Calibration for Offset and	VREF = 4V, VCC = 5V			2		LSB
	Gain Error)	ADC clock = 50 - 200 kHz

		Gain = 200x
		VREF = 4V, VCC = 5V			5		LSB
		ADC clock = 50 - 200 kHz

		Gain =	1x		1.5		%

	Gain Error	Gain =	10x		1.5		%

		Gain = 200x			0.5		%

		Gain = 1x
		VREF = 4V, VCC = 5V			2		LSB
		ADC clock = 50 - 200 kHz

		Gain = 10x
	Offset Error	VREF = 4V, VCC = 5V			3		LSB
		ADC clock = 50 - 200 kHz

		Gain = 200x
		VREF = 4V, VCC = 5V			4		LSB
		ADC clock = 50 - 200 kHz

	Clock Frequency			50		200	kHz

	Conversion Time			65		260	µs

AVCC	Analog Supply Voltage			VCC - 0.3(2)		VCC + 0.3(3)	V
VREF	Reference Voltage			2.0		AVCC - 0.5	V
VIN	Input Voltage			GND		VCC	V
VDIFF	Input Differential Voltage			-VREF/Gain		VREF/Gain	V
	ADC Conversion Output			-511		511	LSB

	Input Bandwidth				4		kHz

328 ATmega128

2467M–AVR–11/04

ATmega128

Table 136. ADC Characteristics, Differential Channels (Continued)

Symbol	Parameter	Condition	Min(1)	Typ(1)	Max(1)	Units
VINT	Internal Voltage Reference		2.3	2.56	2.7	V
RREF	Reference Input Resistance			32		kΩ
RAIN	Analog Input Resistance		55	100		MΩ

Notes: 1. Values are guidelines only.

2.Minimum for AVCC is 2.7V.

3.Maximum for AVCC is 5.5V.

329

2467M–AVR–11/04

External Data Memory Timing

Table 137. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state

				8 MHz Oscillator			Variable Oscillator

	Symbol		Parameter	Min	Max		Min		Max	Unit

0	1/tCLCL		Oscillator Frequency				0.0		16	MHz
1	tLHLL		ALE Pulse Width	115		1.0tCLCL-10				ns
2	t	AVLL	Address Valid A to ALE Low	57.5		0.5t	-5(1)			ns
		AVLL					CLCL
			Address Hold After ALE Low,	5			5
3a	tLLAX_ST		write access	5			5			ns
3a	tLLAX_ST		write access							ns
			Address Hold after ALE Low,	5			5
3b	tLLAX_LD		read access	5			5			ns
3b	tLLAX_LD		read access							ns
4	t	AVLLC	Address Valid C to ALE Low	57.5		0.5t	-5(1)			ns
		AVLLC					CLCL
5	tAVRL		Address Valid to RD Low	115		1.0tCLCL-10				ns
6	tAVWL		Address Valid to WR Low	115		1.0tCLCL-10				ns
7	t	LLWL	ALE Low to WR Low	47.5	67.5	0.5t	-15(2)	0.5t	+5(2)	ns
		LLWL				CLCL			CLCL
8	t	LLRL	ALE Low to RD Low	47.5	67.5	0.5t	-15(2)	0.5t	+5(2)	ns
		LLRL				CLCL			CLCL
9	tDVRH		Data Setup to RD High	40			40			ns
10	tRLDV		Read Low to Data Valid		75			1.0tCLCL-50		ns
11	tRHDX		Data Hold After RD High	0			0			ns
12	tRLRH		RD Pulse Width	115		1.0tCLCL-10				ns
13	t	DVWL	Data Setup to WR Low	42.5		0.5t	-20(1)			ns
		DVWL				CLCL
14	tWHDX		Data Hold After WR High	115		1.0tCLCL-10				ns
15	tDVWH		Data Valid to WR High	125		1.0tCLCL				ns
16	tWLWH		WR Pulse Width	115		1.0tCLCL-10				ns

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 138. External Data Memory Characteristics, 4.5 - 5.5 Volts, 1 Cycle Wait-state

			8 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	16	MHz
10	tRLDV	Read Low to Data Valid		200		2.0tCLCL-50	ns
12	tRLRH	RD Pulse Width	240		2.0tCLCL-10		ns
15	tDVWH	Data Valid to WR High	240		2.0tCLCL		ns
16	tWLWH	WR Pulse Width	240		2.0tCLCL-10		ns

330 ATmega128

2467M–AVR–11/04

ATmega128

Table 139. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

			4 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	16	MHz
10	tRLDV	Read Low to Data Valid		325		3.0tCLCL-50	ns
12	tRLRH	RD Pulse Width	365		3.0tCLCL-10		ns
15	tDVWH	Data Valid to WR High	375		3.0tCLCL		ns
16	tWLWH	WR Pulse Width	365		3.0tCLCL-10		ns

Table 140. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

			4 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	16	MHz
10	tRLDV	Read Low to Data Valid		325		3.0tCLCL-50	ns
12	tRLRH	RD Pulse Width	365		3.0tCLCL-10		ns
14	tWHDX	Data Hold After WR High	240		2.0tCLCL-10		ns
15	tDVWH	Data Valid to WR High	375		3.0tCLCL		ns
16	tWLWH	WR Pulse Width	365		3.0tCLCL-10		ns

Table 141. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state

			4 MHz Oscillator			Variable Oscillator

	Symbol	Parameter	Min	Max		Min		Max	Unit

0	1/tCLCL	Oscillator Frequency				0.0		8	MHz
1	tLHLL	ALE Pulse Width	235		tCLCL-15				ns
2	t	Address Valid A to ALE Low	115		0.5t	-10(1)			ns
	AVLL					CLCL
		Address Hold After ALE Low,	5			5
3a	tLLAX_ST	write access	5			5			ns
3a	tLLAX_ST	write access							ns
		Address Hold after ALE Low,	5			5
3b	tLLAX_LD	read access	5			5			ns
3b	tLLAX_LD	read access							ns
4	t	Address Valid C to ALE Low	115		0.5t	-10(1)			ns
	AVLLC					CLCL
5	tAVRL	Address Valid to RD Low	235		1.0tCLCL-15				ns
6	tAVWL	Address Valid to WR Low	235		1.0tCLCL-15				ns
7	t	ALE Low to WR Low	115	130	0.5t	-10(2)	0.5t	+5(2)	ns
	LLWL					CLCL		CLCL
8	t	ALE Low to RD Low	115	130	0.5t	-10(2)	0.5t	+5(2)	ns
	LLRL					CLCL		CLCL
9	tDVRH	Data Setup to RD High	45			45			ns
10	tRLDV	Read Low to Data Valid		190			1.0tCLCL-60		ns
11	tRHDX	Data Hold After RD High	0			0			ns

331

2467M–AVR–11/04



Table 141. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state					(Continued)

			4 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

12	tRLRH	RD Pulse Width	235		1.0tCLCL-15		ns
13	t	Data Setup to WR Low	105		0.5t -20(1)		ns
	DVWL				CLCL
14	tWHDX	Data Hold After WR High	235		1.0tCLCL-15		ns
15	tDVWH	Data Valid to WR High	250		1.0tCLCL		ns
16	tWLWH	WR Pulse Width	235		1.0tCLCL-15		ns

Table 142. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1
			4 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	8	MHz
10	tRLDV	Read Low to Data Valid		440		2.0tCLCL-60	ns
12	tRLRH	RD Pulse Width	485		2.0tCLCL-15		ns
15	tDVWH	Data Valid to WR High	500		2.0tCLCL		ns
16	tWLWH	WR Pulse Width	485		2.0tCLCL-15		ns

Table 143. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

			4 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	8	MHz
10	tRLDV	Read Low to Data Valid		690		3.0tCLCL-60	ns
12	tRLRH	RD Pulse Width	735		3.0tCLCL-15		ns
15	tDVWH	Data Valid to WR High	750		3.0tCLCL		ns
16	tWLWH	WR Pulse Width	735		3.0tCLCL-15		ns

Table 144. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

			4 MHz Oscillator		Variable Oscillator

	Symbol	Parameter	Min	Max	Min	Max	Unit

0	1/tCLCL	Oscillator Frequency			0.0	8	MHz
10	tRLDV	Read Low to Data Valid		690		3.0tCLCL-60	ns
12	tRLRH	RD Pulse Width	735		3.0tCLCL-15		ns
14	tWHDX	Data Hold After WR High	485		2.0tCLCL-15		ns
15	tDVWH	Data Valid to WR High	750		3.0tCLCL		ns
16	tWLWH	WR Pulse Width	735		3.0tCLCL-15		ns

332 ATmega128

2467M–AVR–11/04

ATmega128

Figure 156. External Memory Timing (SRWn1 = 0, SRWn0 = 0

	T1	T2		T3	T4
System Clock (CLKCPU)
		1
ALE
		4	7
A15:8	Prev. addr.			Address
				15
		2	3a	13
DA7:0	Prev. data	Address	XX	Data
		6		16	14
		6		16
WR
			3b	9	11
DA7:0 (XMBK = 0)		Address		Data
		5		10
			8	12

Figure 157. External Memory Timing (SRWn1 = 0, SRWn0 = 1)

	T1	T2		T3	T4	T5
System Clock (CLKCPU)
		1
ALE
		4	7
A15:8	Prev. addr.			Address
					15
		2	3a	13
DA7:0	Prev. data	Address	XX		Data
		6			16	14
		6			16
WR
			3b		9	11
DA7:0 (XMBK = 0)		Address			Data
		5		10
			8		12

Write

Read

Write

Read

333

2467M–AVR–11/04

Figure 158. External Memory Timing (SRWn1 = 1, SRWn0 = 0)

	T1	T2		T3	T4	T5	T6
System Clock (CLKCPU)
		1
ALE
		4	7
A15:8	Prev. addr.				Address
					15
		2	3a	13
DA7:0	Prev. data	Address	XX		Data
		6			16		14
					16

WR
			3b		9		11
DA7:0 (XMBK = 0)		Address			Data
		5		10
			8		12

Write

Read

Figure 159. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1)

	T1	T2		T3	T4	T5	T6	T7
System Clock (CLKCPU)
		1
ALE
		4	7
A15:8	Prev. addr.				Address
					15
		2	3a	13
DA7:0	Prev. data	Address	XX		Data
		6			16			14
		6			16
WR
			3b		9		11
DA7:0 (XMBK = 0)		Address			Data
		5		10
			8		12

Read Write

Note: 1. The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the RAM (internal or external).

334 ATmega128

2467M–AVR–11/04

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