
- •Features
- •Pin Configurations
- •Overview
- •Block Diagram
- •Pin Descriptions
- •Port A (PA7..PA0)
- •Port B (PB7..PB0)
- •Port C (PC7..PC0)
- •Port D (PD7..PD0)
- •Port E (PE7..PE0)
- •Port F (PF7..PF0)
- •Port G (PG4..PG0)
- •RESET
- •XTAL1
- •XTAL2
- •AVCC
- •AREF
- •AVR CPU Core
- •Introduction
- •Architectural Overview
- •Status Register
- •Stack Pointer
- •Interrupt Response Time
- •SRAM Data Memory
- •Data Memory Access Times
- •EEPROM Data Memory
- •EEPROM Read/Write Access
- •I/O Memory
- •Overview
- •ATmega103 Compatibility
- •Address Latch Requirements
- •Pull-up and Bus-keeper
- •Timing
- •XMEM Register Description
- •Using all Locations of External Memory Smaller than 64 KB
- •Using all 64KB Locations of External Memory
- •Clock Systems and their Distribution
- •Clock Sources
- •Default Clock Source
- •Crystal Oscillator
- •External RC Oscillator
- •External Clock
- •Timer/Counter Oscillator
- •Idle Mode
- •Power-down Mode
- •Power-save Mode
- •Standby Mode
- •Extended Standby Mode
- •Analog to Digital Converter
- •Analog Comparator
- •Brown-out Detector
- •Internal Voltage Reference
- •Watchdog Timer
- •Port Pins
- •Resetting the AVR
- •Reset Sources
- •Power-on Reset
- •External Reset
- •Brown-out Detection
- •Watchdog Reset
- •Watchdog Timer
- •Timed Sequences for Changing the Configuration of the Watchdog Timer
- •Safety Level 0
- •Safety Level 1
- •Safety Level 2
- •Interrupts
- •I/O Ports
- •Introduction
- •Configuring the Pin
- •Reading the Pin Value
- •Unconnected pins
- •Alternate Port Functions
- •Alternate Functions of Port A
- •Alternate Functions of Port B
- •Alternate Functions of Port C
- •Alternate Functions of Port D
- •Alternate Functions of Port E
- •Alternate Functions of Port F
- •Alternate Functions of Port G
- •Register Description for I/O Ports
- •External Interrupts
- •8-bit Timer/Counter0 with PWM and Asynchronous Operation
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Timer/Counter Prescaler
- •16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
- •Overview
- •Registers
- •Definitions
- •Compatibility
- •Counter Unit
- •Input Capture Unit
- •Input Capture Pin Source
- •Noise Canceler
- •Using the Input Capture Unit
- •Output Compare Units
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Internal Clock Source
- •Prescaler Reset
- •External Clock Source
- •8-bit Timer/Counter2 with PWM
- •Overview
- •Registers
- •Definitions
- •Counter Unit
- •Output Compare Unit
- •Force Output Compare
- •Modes of Operation
- •Normal Mode
- •Fast PWM Mode
- •Phase Correct PWM Mode
- •Overview
- •Description
- •Timing Example
- •SS Pin Functionality
- •Slave Mode
- •Master Mode
- •Data Modes
- •USART
- •Dual USART
- •Overview
- •Clock Generation
- •External Clock
- •Synchronous Clock Operation
- •Frame Formats
- •Parity Bit Calculation
- •USART Initialization
- •Sending Frames with 5 to 8 Data Bit
- •Sending Frames with 9 Data Bit
- •Parity Generator
- •Disabling the Transmitter
- •Receiving Frames with 5 to 8 Data Bits
- •Receiving Frames with 9 Data Bits
- •Receiver Error Flags
- •Parity Checker
- •Disabling the Receiver
- •Flushing the Receive Buffer
- •Asynchronous Data Recovery
- •Using MPCM
- •Two-wire Serial Interface
- •Features
- •TWI Terminology
- •Electrical Interconnection
- •Transferring Bits
- •START and STOP Conditions
- •Address Packet Format
- •Data Packet Format
- •Overview of the TWI Module
- •Scl and SDA Pins
- •Bit Rate Generator Unit
- •Bus Interface Unit
- •Address Match Unit
- •Control Unit
- •TWI Register Description
- •Using the TWI
- •Transmission Modes
- •Master Transmitter Mode
- •Master Receiver Mode
- •Slave Receiver Mode
- •Slave Transmitter Mode
- •Miscellaneous States
- •Analog Comparator
- •Analog to Digital Converter
- •Features
- •Operation
- •Starting a Conversion
- •Differential Gain Channels
- •Changing Channel or Reference Selection
- •ADC Input Channels
- •ADC Voltage Reference
- •ADC Noise Canceler
- •Analog Input Circuitry
- •ADC Accuracy Definitions
- •ADC Conversion Result
- •ADLAR = 0:
- •ADLAR = 1:
- •Features
- •Overview
- •TAP Controller
- •PRIVATE0; $8
- •PRIVATE1; $9
- •PRIVATE2; $A
- •PRIVATE3; $B
- •Bibliography
- •Features
- •System Overview
- •Data Registers
- •Bypass Register
- •Device Identification Register
- •Version
- •Part Number
- •Manufacturer ID
- •Reset Register
- •Boundary-scan Chain
- •EXTEST; $0
- •IDCODE; $1
- •SAMPLE_PRELOAD; $2
- •AVR_RESET; $C
- •BYPASS; $F
- •Boundary-scan Chain
- •Scanning the Digital Port Pins
- •Scanning the RESET Pin
- •Scanning the Clock Pins
- •Scanning the ADC
- •Boot Loader Features
- •Application Section
- •Boot Loader Lock Bits
- •Performing a Page Write
- •Using the SPM Interrupt
- •Setting the Boot Loader Lock Bits by SPM
- •Reading the Fuse and Lock Bits from Software
- •Preventing Flash Corruption
- •Simple Assembly Code Example for a Boot Loader
- •Fuse Bits
- •Latching of Fuses
- •Signature Bytes
- •Calibration Byte
- •Signal Names
- •Parallel Programming
- •Enter Programming Mode
- •Chip Erase
- •Programming the Flash
- •Programming the EEPROM
- •Reading the Flash
- •Reading the EEPROM
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Serial Downloading
- •Data Polling Flash
- •Data Polling EEPROM
- •AVR_RESET ($C)
- •PROG_ENABLE ($4)
- •PROG_COMMANDS ($5)
- •PROG_PAGELOAD ($6)
- •PROG_PAGEREAD ($7)
- •Data Registers
- •Reset Register
- •Programming Enable Register
- •Programming Command Register
- •Virtual Flash Page Read Register
- •Programming Algorithm
- •Entering Programming Mode
- •Leaving Programming Mode
- •Performing Chip Erase
- •Programming the Flash
- •Reading the Flash
- •Programming the EEPROM
- •Reading the EEPROM
- •Programming the Fuses
- •Programming the Lock Bits
- •Reading the Signature Bytes
- •Reading the Calibration Byte
- •Electrical Characteristics
- •Absolute Maximum Ratings*
- •DC Characteristics
- •External Clock Drive Waveforms
- •External Clock Drive
- •Two-wire Serial Interface Characteristics
- •ADC Characteristics
- •External Data Memory Timing
- •Active Supply Current
- •Idle Supply Current
- •Power-down Supply Current
- •Power-save Supply Current
- •Standby Supply Current
- •Pin Pull-up
- •Pin Driver Strength
- •Internal Oscillator Speed
- •Current Consumption in Reset and Reset Pulse width
- •Register Summary
- •Instruction Set Summary
- •Ordering Information
- •Packaging Information
- •Errata
- •ATmega128 Rev. I
- •ATmega128 Rev. H
- •ATmega128 Rev. G
- •ATmega128 Rev. F
- •Changes from Rev. 2467L-05/04 to Rev. 2467M-11/04
- •Changes from Rev. 2467K-03/04 to Rev. 2467L-05/04
- •Changes from Rev. 2467J-12/03 to Rev. 2467K-03/04
- •Changes from Rev. 2467I-09/03 to Rev. 2467J-12/03
- •Changes from Rev. 2467H-02/03 to Rev. 2467I-09/03
- •Changes from Rev. 2467G-09/02 to Rev. 2467H-02/03
- •Changes from Rev. 2467F-09/02 to Rev. 2467G-09/02
- •Changes from Rev. 2467E-04/02 to Rev. 2467F-09/02
- •Changes from Rev. 2467D-03/02 to Rev. 2467E-04/02
- •Changes from Rev. 2467C-02/02 to Rev. 2467D-03/02
- •Changes from Rev. 2467B-09/01 to Rev. 2467C-02/02
- •Table of Contents

External Clock
zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the Internal Oscillator. Writing $FF to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0, 2.0, 4.0, or 8.0 MHz. Tuning to other values is not guaranteed, as indicated in Table 15.
Table 15. Internal RC Oscillator Frequency Range.
|
Min Frequency in Percentage of |
Max Frequency in Percentage of |
OSCCAL Value |
Nominal Frequency (%) |
Nominal Frequency (%) |
|
|
|
$00 |
50 |
100 |
|
|
|
$7F |
75 |
150 |
|
|
|
$FF |
100 |
200 |
|
|
|
To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 21. To run the device on an external clock, the CKSEL fuses must be programmed to “0000”. By programming the CKOPT fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND.
Figure 21. External Clock Drive Configuration
EXTERNAL
CLOCK
SIGNAL
When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 16.
Table 16. Start-up Times for the External Clock Selection
|
Start-up Time from Power- |
Additional Delay from |
|
SUT1..0 |
down and Power-save |
Reset (VCC = 5.0V) |
Recommended Usage |
00 |
6 CK |
– |
BOD enabled |
|
|
|
|
01 |
6 CK |
4.1 ms |
Fast rising power |
|
|
|
|
10 |
6 CK |
65 ms |
Slowly rising power |
|
|
|
|
11 |
|
Reserved |
|
|
|
|
|
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency.
40 ATmega128
2467M–AVR–11/04