|
D a t a S h e e t |
|
Table 12.1 |
Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
44 |
Table 13.1 |
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
44 |
Table 14.1 |
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
45 |
Table 15.1 |
DC Characteristics, CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
46 |
Table 16.1 |
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
48 |
Table 17.1 |
Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
52 |
Table 17.2 |
Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
56 |
Table 17.3 |
Alternate CE# Controlled Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
58 |
List of Figures |
|
|
Figure 3.1 |
40-pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
.7 |
Figure 3.2 |
48-pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
.7 |
Figure 3.3 |
Model 00 48-ball FBGA (Top View, Balls Facing Down) . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
.8 |
Figure 3.4 |
Models 03, 04 48-ball FBGA (Top View, Balls Facing Down) . . . . . . . . . . . . . . . . . . . . . . . . . |
.9 |
Figure 5.1 |
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
10 |
Figure 7.1 |
In-System Sector Protect/Unprotect Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
25 |
Figure 7.2 |
Temporary Sector Unprotect Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
26 |
Figure 8.1 |
Secured Silicon Sector Protect Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
28 |
Figure 11.1 |
Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
34 |
Figure 11.2 |
Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
36 |
Figure 12.1 |
Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
41 |
Figure 12.2 |
Toggle Bit Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
43 |
Figure 13.1 |
Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
45 |
Figure 13.2 |
Maximum Positive Overshoot Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
45 |
Figure 15.1 ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) . . . . . . . . . . . . . . . . |
47 |
|
Figure 15.2 Typical ICC1 vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
47 |
|
Figure 16.1 |
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
48 |
Figure 16.2 |
Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
48 |
Figure 17.1 |
Read Operations Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
49 |
Figure 17.2 |
RESET# Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
50 |
Figure 17.3 |
BYTE# Timings for Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
51 |
Figure 17.4 |
BYTE# Timings for Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
51 |
Figure 17.5 |
Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
53 |
Figure 17.6 |
Chip/Sector Erase Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
53 |
Figure 17.7 Back to Back Read/Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
54 |
|
Figure 17.8 Data# Polling Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
54 |
|
Figure 17.9 |
Toggle Bit Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
55 |
Figure 17.10 |
DQ2 vs. DQ6 for Erase and Erase Suspend Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
55 |
Figure 17.11 |
Temporary Sector Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
56 |
Figure 17.12 |
Accelerated Program Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
56 |
Figure 17.13 |
Sector Protect/Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
57 |
Figure 17.14 |
Alternate CE# Controlled Write Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
59 |
January 19, 2007 S29AL032D_00_A9 |
S29AL032D |
5 |
D a t a S h e e t
1.Product Selector Guide
Family Part Number |
|
|
S29AL032D |
|
|
|
|
|
|
Speed Option |
Voltage Range: VCC = 2.7–3.6 V |
70 |
|
90 |
Max access time, ns (tACC) |
|
70 |
|
90 |
Max CE# access time, ns (tCE) |
70 |
|
90 |
|
Max OE# access time, ns (tOE) |
30 |
|
35 |
|
Note
See AC Characteristics on page 49 for full specifications.
2. Block Diagram
|
RY/BY# |
|
|
DQ0–DQ15 (A-1), (DQ0-DQ7 Model 00) |
||
|
|
|
|
|
|
|
VCC |
|
|
Sector Switches |
|
|
|
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
RESET# |
|
|
Erase Voltage |
|
|
Input/Output |
|
|
Generator |
|
|
Buffers |
|
|
|
|
|
|
||
WE# |
State |
|
|
|
|
|
BYTE# |
Control |
|
|
|
|
|
|
|
|
|
|
|
|
|
Command |
|
|
|
|
|
|
Register |
PGM Voltage |
|
|
|
|
|
|
|
|
|
|
|
|
|
Generator |
|
|
|
|
|
|
|
Chip Enable |
STB |
Data |
|
|
|
|
Latch |
|||
CE# |
|
|
Output Enable |
|||
|
|
|
|
|||
OE# |
|
|
|
Logic |
|
|
|
|
|
|
|
|
|
|
|
|
STB |
Y-Decoder |
|
Y-Gating |
|
|
|
|
|
|
|
|
VCC Detector |
Timer |
Latch |
|
|
|
|
|
|
|
|
|
|
|
|
|
Address |
X-Decoder |
|
Cell Matrix |
A0–A20 (A0-A21 Model 00) |
|
|
|
|
||
|
|
|
|
|
||
6 |
S29AL032D |
S29AL032D_00_A9 January 19, 2007 |