D a t a S h e e t
17.5Temporary Sector Unprotect
Table 17.2 Temporary Sector Unprotect
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JEDEC |
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Std. |
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Description |
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All Speed Options |
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Unit |
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tVIDR |
VID Rise and Fall Time (See Note) |
Min |
500 |
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ns |
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tRSP |
RESET# Setup Time for Temporary Sector |
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4 |
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µs |
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Unprotect |
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Note |
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Not 100% tested. |
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Figure 17.11 Temporary Sector Unprotect Timing Diagram |
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RESET# |
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12 V |
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0 or 3 V |
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Program or Erase Command Sequence |
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CE# |
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tVIDR |
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tVIDR |
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WE# |
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tRSP |
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RY/BY# |
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Figure 17.12 Accelerated Program Timing Diagram |
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VHH |
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VIL or VIH |
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VIL or VIH |
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WP#/ACC |
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tVHH |
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tVHH |
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56 |
S29AL032D |
S29AL032D_00_A9 January 19, 2007 |
D a t a S h e e t
Figure 17.13 Sector Protect/Unprotect Timing Diagram
VID
VIH
RESET#
SA, A6, |
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Valid* |
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Valid* |
Valid* |
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A1, A0 |
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Sector Protect/Unprotect |
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Verify |
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Data |
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60h |
60h |
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40h |
Status |
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Sector Protect: 150 µs |
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1 µs |
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CE# |
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Sector Unprotect: 15 ms |
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WE# |
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OE#
Note
For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
January 19, 2007 S29AL032D_00_A9 |
S29AL032D |
57 |
D a t a S h e e t
17.6Alternate CE# Controlled Erase/Program Operations
Table 17.3 Alternate CE# Controlled Erase/Program Operations
Parameter |
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Speed Options |
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JEDEC |
Std. |
Description |
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70 |
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90 |
Unit |
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tAVAV |
tWC |
Write Cycle Time (Note 1) |
Min |
70 |
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90 |
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tAVEL |
tAS |
Address Setup Time |
Min |
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tELAX |
tAH |
Address Hold Time |
Min |
45 |
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tDVEH |
tDS |
Data Setup Time |
Min |
35 |
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45 |
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tEHDX |
tDH |
Data Hold Time |
Min |
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tOES |
Output Enable Setup Time |
Min |
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0 |
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tGHEL |
tGHEL |
Read Recovery Time Before Write |
Min |
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0 |
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(OE# High to WE# Low) |
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tWLEL |
tWS |
WE# Setup Time |
Min |
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0 |
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tEHWH |
tWH |
WE# Hold Time |
Min |
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tELEH |
tCP |
CE# Pulse Width |
Min |
35 |
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tEHEL |
tCPH |
CE# Pulse Width High |
Min |
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tSR/W |
Latency Between Read and Write Operations |
Min |
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tWHWH1 |
tWHWH1 |
Programming Operation (Note 2) |
Byte |
Typ |
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9 |
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tWHWH1 |
tWHWH1 |
Accelerated Programming Operation, |
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tWHWH2 |
tWHWH2 |
Sector Erase Operation (Note 2) |
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Notes
1.Not 100% tested.
2.See the Erase and Programming Performance on page 60 section for more information.
58 |
S29AL032D |
S29AL032D_00_A9 January 19, 2007 |
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D a t a S h e e t |
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Figure 17.14 Alternate CE# Controlled Write Operation Timings |
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555 for program |
PA for program |
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2AA for erase |
SA for sector erase |
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555 for chip erase |
Data# Polling |
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PA |
tWC |
tAS |
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tAH |
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tWH |
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WE# |
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tGHEL |
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OE# |
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tCP |
tWHWH1 or 2 |
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CE# |
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tWS |
tCPH |
tBUSY |
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tDS |
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tDH |
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Data |
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DQ7# DOUT |
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tRH |
A0 for program |
PD for program |
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55 for erase |
30 for sector erase |
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10 for chip erase |
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RESET#
RY/BY#
Notes
1.PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device.
2.Figure indicates the last two bus cycles of the command sequence.
3.Word mode address used as an example.
January 19, 2007 S29AL032D_00_A9 |
S29AL032D |
59 |