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Национальный исследовательский университет «МИЭТ»

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Программирование логических интегральных схем

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ПЛИС / FPGA Sixth Flash / spansion inc_s29al032d-329471.pdf

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D a t a S h e e t

17. AC Characteristics

17.1Read Operations

Parameter						Speed Options

JEDEC	Std	Description		Test Setup		70		90	Unit

tAVAV	tRC	Read Cycle Time (Note 1)			Min	70		90	ns
tAVQV	tACC	Address to Output Delay		CE# = VIL	Max	70		90	ns
tAVQV	tACC	Address to Output Delay		OE# = VIL	Max	70		90	ns
				OE# = VIL
tELQV	tCE	Chip Enable to Output Delay		OE# = VIL	Max	70		90	ns
tGLQV	tOE	Output Enable to Output Delay			Max	30		35	ns
tEHQZ	tDF	Chip Enable to Output High Z (Note 1)			Max		16		ns
tGHQZ	tDF	Output Enable to Output High Z (Note 1)			Max		16		ns
	tSR/W	Latency Between Read and Write Operations			Min		20		ns
	tOEH	Output Enable	Read		Min		0		ns
		Output Enable
		Hold Time (Note 1)	Toggle and Data# Polling		Min		10		ns
		Hold Time (Note 1)	Toggle and Data# Polling		Min		10		ns

tAXQX	tOH	Output Hold Time From Addresses, CE# or OE#, Whichever			Min		0		ns
tAXQX	tOH	Occurs First (Note 1)			Min		0		ns

Notes

1.Not 100% tested.

2.See Figure 16.1 on page 48 and Table 16.1 on page 48 for test specifications.

	Figure 17.1	Read Operations Timings
		tRC
Addresses		Addresses Stable
		tACC
CE#
		tDF
OE#	tSR/W	tOE
OE#	tSR/W
	tOEH
WE#		tCE
		tCE
		tOH
	HIGH Z	HIGH Z
Outputs		Output Valid
RESET#
RY/BY#	0 V
	0 V

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D a t a S h e e t

17.2Hardware Reset (RESET#)

Parameter

JEDEC	Std.	Description	Test Setup		All Speed Options	Unit

	tREADY	RESET# Pin Low (During Embedded Algorithms) to		Max	20	µs
	tREADY	Read or Write (See Note)		Max	20	µs
	tREADY	RESET# Pin Low (NOT During Embedded		Max	500	ns
	tREADY	Algorithms) to Read or Write (See Note)		Max	500	ns
	tRP	RESET# Pulse Width		Min	500	ns
	tRH	RESET# High Time Before Read (See Note)		Min	50	ns
	tRPD	RESET# Low to Standby Mode		Min	20	µs
	tRB	RY/BY# Recovery Time		Min	0	ns

Note

Not 100% tested.

Figure 17.2 RESET# Timings

RY/BY#

CE#, OE#

tRH

RESET#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

tReady

RY/BY#

tRB

CE#, OE#

tRH

RESET#

tRP

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D a t a S h e e t

17.3Word/Byte Configuration (BYTE#) (Models 03, 04 Only)

	Parameter				Speed Options

JEDEC		Std.	Description		70		90	Unit

		tELFL/tELFH	CE# to BYTE# Switching Low or High	Max		5		ns
		tFLQZ	BYTE# Switching Low to Output HIGH Z	Max		16		ns
		tFHQV	BYTE# Switching High to Output Active	Min	70		90	ns

BYTE# Switching from word to byte mode

BYTE# Switching from byte to word mode

Note

Figure 17.3 BYTE# Timings for Read Operations

CE#

OE#

BYTE#

tELFL

DQ0–DQ14 Data Output Data Output (DQ0–DQ14) (DQ0–DQ7)

DQ15/A-1	DQ15	Address

	Output	Input

tFLQZ

tELFH

BYTE#

DQ0–DQ14	Data Output	Data Output
DQ0–DQ14	Data Output	Data Output
	(DQ0–DQ7)	(DQ0–DQ14)
	(DQ0–DQ7)	(DQ0–DQ14)
DQ15/A-1	Address	DQ15




	Input	Output
	Input	Output

tFHQV

Figure 17.4 BYTE# Timings for Write Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#	tSET



	(tAS)	tHOLD (tAH)

Refer to the Erase/Program Operations table for tAS and tAH specifications.

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D a t a S h e e t

17.4Erase/Program Operations

Table 17.1 Erase/Program Operations

Parameter					Speed Options

JEDEC	Std.	Description			70		90	Unit

tAVAV	tWC	Write Cycle Time (Note 1)		Min	70		90	ns
tAVWL	tAS	Address Setup Time		Min		0		ns
tWLAX	tAH	Address Hold Time		Min	45		45	ns
tDVWH	tDS	Data Setup Time		Min	35		45	ns
tWHDX	tDH	Data Hold Time		Min		0		ns
	tOES	Output Enable Setup Time		Min		0		ns
tGHWL	tGHWL	Read Recovery Time Before Write		Min		0		ns
tGHWL	tGHWL	(OE# High to WE# Low)		Min		0		ns
tELWL	tCS	CE# Setup Time		Min		0		ns
tWHEH	tCH	CE# Hold Time		Min		0		ns
tWLWH	tWP	Write Pulse Width		Min	35		35	ns
tWHWL	tWPH	Write Pulse Width High		Min		30		ns
	tSR/W	Latency Between Read and Write Operations		Min		20		ns
tWHWH1	tWHWH1	Programming Operation (Note 2)	Byte	Typ		9		µs

			Word	Typ		11
			Word	Typ		11

tWHWH1	tWHWH1	Accelerated Programming Operation, Word or Byte (Note 2)		Typ		7		µs
tWHWH2	tWHWH2	Sector Erase Operation (Note 2)		Typ		0.7		sec
	tVCS	VCC Setup Time (Note 1)		Min		50		µs
	tRB	Recovery Time from RY/BY#		Min		0		ns
	tBUSY	Program/Erase Valid to RY/BY# Delay		Max		90		ns

Notes

1.Not 100% tested.

2.See Erase and Programming Performance on page 60 for more information.

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D a t a S h e e t

Addresses

CE#

OE#

WE#

Data

RY/BY#

VCC

Figure 17.5	Program Operation Timings
Program Command Sequence (last two cycles)		Read Status Data (last two cycles)
tWC	tAS

555h	PA	PA	PA
	tAH
tCH
tWP		tWHWH1
tWPH
tCS
tDS
tDH
A0h	PD	Status	DOUT
	tBUSY		tRB

tVCS

Notes

1.PA = program address, PD = program data, DOUT is the true data at the program address.

2.Illustration shows device in word mode.

Figure 17.6 Chip/Sector Erase Operation Timings

Erase Command Sequence (last two cycles)

Read Status Data

	tWC	tAS
Addresses	2AAh	SA	VA	VA
		555h for chip erase	tAH
			tAH
CE#
OE#		tCH
		tWP

WE#

tWPH	tWHWH2
tCS

	tDS
	tDH
Data	55h	30h	In	Complete
Data	55h	30h	Progress	Complete
		10 for Chip Erase

tBUSY

tRB

RY/BY#

tVCS

VCC

Notes

1.SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 40).

2.Illustration shows device in word mode.

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D a t a S h e e t

Figure 17.7

Back to Back Read/Write Cycle Timing

Addresses

tWC

tRC

tACC

tAH

tCPH

CE#

tCE

OE#

tSR/W

tOE

tCP

tGHWL

WE#

tWP

tDF

tWDH

tDS

Data

tDH

tOH

Valid In

Valid Out

Valid In

Valid Out

		Figure 17.8	Data# Polling Timings (During Embedded Algorithms)
		tRC
Addresses		VA		VA		VA
		tACC
CE#		tCE
CE#
	tCH	tOE
		tOE
OE#
		tOEH	tDF
WE#
			tOH
DQ7						High Z
DQ7			Complement	Complement	True	Valid Data
DQ0–DQ6						High Z
DQ0–DQ6			Status Data	Status Data	True	Valid Data
			Status Data	Status Data	True	Valid Data
	tBUSY
RY/BY#

Note

VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

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D a t a S h e e t

Figure 17.9 Toggle Bit Timings (During Embedded Algorithms)

tRC

Addresses

tACC

CE#		tCE
CE#
	tCH	tOE
		tOE
OE#
	tOEH
WE#
DQ6/DQ2		High Z
DQ6/DQ2
	tBUSY
RY/BY#
Note

	tDF




	tOH
	tOH
Valid Status		Valid Status
Valid Status		Valid Status
(first read)		(second read)

Valid Status		Valid Data

(stops toggling)

VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 17.10 DQ2 vs. DQ6 for Erase and Erase Suspend Operations

Enter

Erase

Enter Erase

Erase

Embedded

Suspend

Suspend Program

Erasing

Resume

WE#

Erase

Erase Suspend

Erase

Erase Suspend

Erase

Read

Suspend

Complete

Program

Read

DQ6

DQ2

Note

The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.

January 19, 2007 S29AL032D_00_A9

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