
- •Distinctive Characteristics
- •General Description
- •S29AL032D Features
- •Table of Contents
- •List of Tables
- •List of Figures
- •1. Product Selector Guide
- •2. Block Diagram
- •3. Connection Diagrams
- •3.1 FBGA Package for Model 00 Only
- •3.2 FBGA Package for Models 03, 04 Only
- •3.3 Special Handling Instructions
- •4. Pin Configuration
- •5. Logic Symbols
- •6. Ordering Information
- •6.1 S29AL032D Standard Products
- •6.2 Valid Combinations
- •7. Device Bus Operations
- •7.1 Word/Byte Configuration (Models 03, 04 Only)
- •7.2 Requirements for Reading Array Data
- •7.3 Writing Commands/Command Sequences
- •7.4 Program and Erase Operation Status
- •7.5 Accelerated Program Operation
- •7.6 Standby Mode
- •7.7 Automatic Sleep Mode
- •7.8 RESET#: Hardware Reset Pin
- •7.9 Output Disable Mode
- •7.10 Sector Addresss Tables
- •7.11 Autoselect Mode
- •7.12 Sector Protection/Unprotection
- •7.14 Temporary Sector Unprotect
- •8. Secured Silicon Sector Flash Memory Region
- •9. Hardware Data Protection
- •9.2 Write Pulse “Glitch” Protection
- •9.3 Logical Inhibit
- •10. Common Flash Memory Interface (CFI)
- •11. Command Definitions
- •11.1 Reading Array Data
- •11.2 Reset Command
- •11.3 Autoselect Command Sequence
- •11.5 Word/Byte Program Command Sequence
- •11.6 Unlock Bypass Command Sequence
- •11.7 Chip Erase Command Sequence
- •11.8 Sector Erase Command Sequence
- •11.9 Erase Suspend/Erase Resume Commands
- •11.10 Command Definitions Table
- •12. Write Operation Status
- •12.1 DQ7: Data# Polling
- •12.2 RY/BY#: Ready/Busy#
- •12.3 DQ6: Toggle Bit I
- •12.4 DQ2: Toggle Bit II
- •12.5 Reading Toggle Bits DQ6/DQ2
- •12.6 DQ5: Exceeded Timing Limits
- •12.7 DQ3: Sector Erase Timer
- •13. Absolute Maximum Ratings
- •14. Operating Ranges
- •15. DC Characteristics
- •15.1 Zero Power Flash
- •16. Test Conditions
- •16.1 Key to Switching Waveforms
- •17. AC Characteristics
- •17.1 Read Operations
- •17.2 Hardware Reset (RESET#)
- •17.3 Word/Byte Configuration (BYTE#) (Models 03, 04 Only)
- •17.4 Erase/Program Operations
- •17.5 Temporary Sector Unprotect
- •17.6 Alternate CE# Controlled Erase/Program Operations
- •18. Erase and Programming Performance
- •19. TSOP and BGA Pin Capacitance
- •20. Physical Dimensions
- •21. Revision History

D a t a S h e e t
16. Test Conditions
Figure 16.1 Test Setup
3.3 V
2.7 kΩ
Device
Under
Test
CL |
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6.2 kΩ |
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Note
Diodes are IN3064 or equivalent.
Table 16.1 |
Test Specifications |
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Speed Option |
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70 |
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90 |
Unit |
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Output Load |
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1 TTL gate |
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Output Load Capacitance, CL |
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30 |
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100 |
pF |
(including jig capacitance) |
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Input Rise and Fall Times |
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5 |
ns |
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Input Pulse Levels |
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0.0 or VCC |
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Input timing measurement reference levels |
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0.5 VCC |
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Output timing measurement reference levels |
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0.5 VCC |
V |
16.1Key to Switching Waveforms
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Steady |
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Changing from H to L |
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Changing from L to H |
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Don’t Care, Any Change Permitted |
Changing, State Unknown |
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Does Not Apply |
Center Line is High Impedance State (High Z) |
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Figure 16.2 |
Input Waveforms and Measurement Levels |
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VCC |
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0.5 VCC |
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0.5 VCC |
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Measurement Level |
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Output |
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0.0 V |
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48 |
S29AL032D |
S29AL032D_00_A9 January 19, 2007 |