- •Distinctive Characteristics
- •General Description
- •S29AL032D Features
- •1. Product Selector Guide
- •2. Block Diagram
- •3. Connection Diagrams
- •Figure 3.1 40-pin Standard TSOP
- •3.1 FBGA Package for Model 00 Only
- •Figure 3.3 Model 00 48-ball FBGA (Top View, Balls Facing Down)
- •3.2 FBGA Package for Models 03, 04 Only
- •Figure 3.4 Models 03, 04 48-ball FBGA (Top View, Balls Facing Down)
- •3.3 Special Handling Instructions
- •4. Pin Configuration
- •5. Logic Symbols
- •6. Ordering Information
- •6.1 S29AL032D Standard Products
- •6.2 Valid Combinations
- •7. Device Bus Operations
- •Table 8. S29AL032D Device Bus Operations
- •7.1 Word/Byte Configuration (Models 03, 04 Only)
- •7.2 Requirements for Reading Array Data
- •7.4 Program and Erase Operation Status
- •7.5 Accelerated Program Operation
- •7.6 Standby Mode
- •7.7 Automatic Sleep Mode
- •7.8 RESET#: Hardware Reset Pin
- •7.9 Output Disable Mode
- •7.10 Sector Addresss Tables
- •Table 8. Model 00 Sector Addresses (Sheet 1 of 2)
- •Table 9. Model 00 Secured Silicon Sector Addresses
- •Table 10. Model 03 Sector Addresses (Sheet 1 of 2)
- •Table 11. Model 03 Secured Silicon Sector Addresses
- •Table 12. Model 04 Sector Addresses (Sheet 1 of 2)
- •Table 13. Model 04 Secured Silicon Sector Addresses
- •7.11 Autoselect Mode
- •Table 8. S29AL032D Autoselect Codes (High Voltage Method)
- •7.12 Sector Protection/Unprotection
- •Table 8. Sector Block Addresses for Protection/Unprotection — Model 00
- •Table 9. Sector Block Addresses for Protection/Unprotection — Model 03 (Sheet 1 of 2)
- •7.13 Write Protect (WP#) — Models 03, 04 Only
- •7.14 Temporary Sector Unprotect
- •8. Secured Silicon Sector Flash Memory Region
- •Figure 8.1 Secured Silicon Sector Protect Verify
- •9. Hardware Data Protection
- •9.1 Low VCC Write Inhibit
- •9.2 Write Pulse “Glitch” Protection
- •9.3 Logical Inhibit
- •10. Common Flash Memory Interface (CFI)
- •Table 11. CFI Query Identification String
- •Table 12. System Interface String
- •Table 13. Device Geometry Definition
- •11. Command Definitions
- •11.1 Reading Array Data
- •11.2 Reset Command
- •11.3 Autoselect Command Sequence
- •11.6 Unlock Bypass Command Sequence
- •Figure 11.1 Program Operation
- •11.7 Chip Erase Command Sequence
- •11.8 Sector Erase Command Sequence
- •Figure 11.2 Erase Operation
- •11.10 Command Definitions Table
- •Table 12. S29AL032D Command Definitions — Model 00
- •12. Write Operation Status
- •12.1 DQ7: Data# Polling
- •Figure 12.1 Data# Polling Algorithm
- •12.2 RY/BY#: Ready/Busy#
- •12.3 DQ6: Toggle Bit I
- •12.4 DQ2: Toggle Bit II
- •12.5 Reading Toggle Bits DQ6/DQ2
- •Figure 12.2 Toggle Bit Algorithm
- •12.6 DQ5: Exceeded Timing Limits
- •12.7 DQ3: Sector Erase Timer
- •Table 13. Write Operation Status
- •13. Absolute Maximum Ratings
- •Table 14. Absolute Maximum Ratings
- •14. Operating Ranges
- •Table 15. Operating Ranges
- •15. DC Characteristics
- •Table 16. DC Characteristics, CMOS Compatible
- •15.1 Zero Power Flash
- •Figure 15.2 Typical ICC1 vs. Frequency
- •16. Test Conditions
- •16.1 Key to Switching Waveforms
- •Figure 16.1 Input Waveforms and Measurement Levels
- •17. AC Characteristics
- •17.1 Read Operations
- •Figure 17.1 Read Operations Timings
- •17.2 Hardware Reset (RESET#)
- •17.3 Word/Byte Configuration (BYTE#) (Models 03, 04 Only)
- •Figure 17.3 BYTE# Timings for Read Operations
- •Figure 17.4 BYTE# Timings for Write Operations
- •17.4 Erase/Program Operations
- •Table 18. Erase/Program Operations
- •Figure 18.1 Program Operation Timings
- •Figure 18.3 Back to Back Read/Write Cycle Timing
- •Figure 18.4 Data# Polling Timings (During Embedded Algorithms)
- •Figure 18.5 Toggle Bit Timings (During Embedded Algorithms)
- •17.5 Temporary Sector Unprotect
- •Table 18. Temporary Sector Unprotect
- •Figure 18.1 Temporary Sector Unprotect Timing Diagram
- •Figure 18.3 Sector Protect/Unprotect Timing Diagram
- •17.6 Alternate CE# Controlled Erase/Program Operations
- •Figure 18.1 Alternate CE# Controlled Write Operation Timings
- •18. Erase and Programming Performance
- •19. TSOP and BGA Pin Capacitance
- •19.3 VBN048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 10.0 x 6.0 mm
- •20. Document History Page
- •RYSU
- •RYSU
- •RYSU
- •RYSU
- •RYSU
- •RYSU
- •Sales, Solutions, and Legal Information
- •Worldwide Sales and Design Support
- •Products
- •PSoC® Solutions
- •Cypress Developer Community
- •Technical Support
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S29AL032D |
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19.3 |
VBN048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 10.0 x 6.0 mm |
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D |
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A |
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D1 |
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e |
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e |
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6 |
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5 |
7 |
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E |
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4 |
SE |
E1 |
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+0.20 0.50- |
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3 |
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1.00 |
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Ø0.50 |
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2 |
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1 |
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H |
G |
F |
E |
D |
C B A |
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+0.20 |
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B |
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Design |
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1.00 |
-0.50 |
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A1 ID. |
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Øb |
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Ø0.08 M C |
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Ø0.15 M C A B |
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A |
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A2 |
0.10 C |
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New |
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A1 |
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SEATING PLANE |
C |
0.08 C |
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Recommended |
for |
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PACKAGE |
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VBN 048 |
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NOTES: |
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1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. |
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JEDEC |
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N/A |
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2. ALL DIMENSIONS ARE IN MILLIMETERS. |
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10.00 mm x 6.00 mm NOM |
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3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT |
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PACKAGE |
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AS NOTED). |
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SYMBOL |
MIN |
NOM |
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MAX |
NOTE |
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4. e REPRESENTS THE SOLDER BALL GRID PITCH. |
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A |
--- |
--- |
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1.00 |
OVERALL THICKNESS |
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5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE |
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A1 |
0.17 |
--- |
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BALL HEIGHT |
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"D" DIRECTION. |
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A2 |
0.62 |
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0.73 |
BODY THICKNESS |
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SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE |
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D |
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10.00 BSC. |
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BODY SIZE |
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"E" DIRECTION. |
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N IS THE TOTAL NUMBER OF SOLDER BALLS. |
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E |
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6.00 BSC. |
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BODY SIZE |
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6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL |
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D1 |
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5.60 BSC. |
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BALL FOOTPRINT |
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Not |
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DIAMETER IN A PLANE PARALLEL TO DATUM C. |
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E1 |
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4.00 BSC. |
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BALL FOOTPRINT |
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7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS |
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MD |
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8 |
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ROW MATRIX SIZE D DIRECTION |
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A AND B AND DEFINE THE POSITION OF THE CENTER |
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ME |
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6 |
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ROW MATRIX SIZE E DIRECTION |
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SOLDER BALL IN THE OUTER ROW. |
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WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN |
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N |
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48 |
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TOTAL BALL COUNT |
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THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, |
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fb |
0.35 |
--- |
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0.45 |
BALL DIAMETER |
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RESPECTIVELY, SD OR SE = 0.000. |
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e |
0.80 BSC. |
BALL PITCH |
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WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN |
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THE OUTER ROW, SD OR SE = e/2 |
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SD / SE |
0.40 BSC. |
SOLDER BALL PLACEMENT |
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8. |
NOT USED. |
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NONE |
DEPOPULATED SOLDER BALLS |
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9. |
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED |
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BALLS. |
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10 |
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK |
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MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. |
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3425\ 16-038.25 |
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Document Number: 002-02003 Rev. *B |
Page 61 of 64 |
