- •Distinctive Characteristics
- •General Description
- •S29AL032D Features
- •1. Product Selector Guide
- •2. Block Diagram
- •3. Connection Diagrams
- •Figure 3.1 40-pin Standard TSOP
- •3.1 FBGA Package for Model 00 Only
- •Figure 3.3 Model 00 48-ball FBGA (Top View, Balls Facing Down)
- •3.2 FBGA Package for Models 03, 04 Only
- •Figure 3.4 Models 03, 04 48-ball FBGA (Top View, Balls Facing Down)
- •3.3 Special Handling Instructions
- •4. Pin Configuration
- •5. Logic Symbols
- •6. Ordering Information
- •6.1 S29AL032D Standard Products
- •6.2 Valid Combinations
- •7. Device Bus Operations
- •Table 8. S29AL032D Device Bus Operations
- •7.1 Word/Byte Configuration (Models 03, 04 Only)
- •7.2 Requirements for Reading Array Data
- •7.4 Program and Erase Operation Status
- •7.5 Accelerated Program Operation
- •7.6 Standby Mode
- •7.7 Automatic Sleep Mode
- •7.8 RESET#: Hardware Reset Pin
- •7.9 Output Disable Mode
- •7.10 Sector Addresss Tables
- •Table 8. Model 00 Sector Addresses (Sheet 1 of 2)
- •Table 9. Model 00 Secured Silicon Sector Addresses
- •Table 10. Model 03 Sector Addresses (Sheet 1 of 2)
- •Table 11. Model 03 Secured Silicon Sector Addresses
- •Table 12. Model 04 Sector Addresses (Sheet 1 of 2)
- •Table 13. Model 04 Secured Silicon Sector Addresses
- •7.11 Autoselect Mode
- •Table 8. S29AL032D Autoselect Codes (High Voltage Method)
- •7.12 Sector Protection/Unprotection
- •Table 8. Sector Block Addresses for Protection/Unprotection — Model 00
- •Table 9. Sector Block Addresses for Protection/Unprotection — Model 03 (Sheet 1 of 2)
- •7.13 Write Protect (WP#) — Models 03, 04 Only
- •7.14 Temporary Sector Unprotect
- •8. Secured Silicon Sector Flash Memory Region
- •Figure 8.1 Secured Silicon Sector Protect Verify
- •9. Hardware Data Protection
- •9.1 Low VCC Write Inhibit
- •9.2 Write Pulse “Glitch” Protection
- •9.3 Logical Inhibit
- •10. Common Flash Memory Interface (CFI)
- •Table 11. CFI Query Identification String
- •Table 12. System Interface String
- •Table 13. Device Geometry Definition
- •11. Command Definitions
- •11.1 Reading Array Data
- •11.2 Reset Command
- •11.3 Autoselect Command Sequence
- •11.6 Unlock Bypass Command Sequence
- •Figure 11.1 Program Operation
- •11.7 Chip Erase Command Sequence
- •11.8 Sector Erase Command Sequence
- •Figure 11.2 Erase Operation
- •11.10 Command Definitions Table
- •Table 12. S29AL032D Command Definitions — Model 00
- •12. Write Operation Status
- •12.1 DQ7: Data# Polling
- •Figure 12.1 Data# Polling Algorithm
- •12.2 RY/BY#: Ready/Busy#
- •12.3 DQ6: Toggle Bit I
- •12.4 DQ2: Toggle Bit II
- •12.5 Reading Toggle Bits DQ6/DQ2
- •Figure 12.2 Toggle Bit Algorithm
- •12.6 DQ5: Exceeded Timing Limits
- •12.7 DQ3: Sector Erase Timer
- •Table 13. Write Operation Status
- •13. Absolute Maximum Ratings
- •Table 14. Absolute Maximum Ratings
- •14. Operating Ranges
- •Table 15. Operating Ranges
- •15. DC Characteristics
- •Table 16. DC Characteristics, CMOS Compatible
- •15.1 Zero Power Flash
- •Figure 15.2 Typical ICC1 vs. Frequency
- •16. Test Conditions
- •16.1 Key to Switching Waveforms
- •Figure 16.1 Input Waveforms and Measurement Levels
- •17. AC Characteristics
- •17.1 Read Operations
- •Figure 17.1 Read Operations Timings
- •17.2 Hardware Reset (RESET#)
- •17.3 Word/Byte Configuration (BYTE#) (Models 03, 04 Only)
- •Figure 17.3 BYTE# Timings for Read Operations
- •Figure 17.4 BYTE# Timings for Write Operations
- •17.4 Erase/Program Operations
- •Table 18. Erase/Program Operations
- •Figure 18.1 Program Operation Timings
- •Figure 18.3 Back to Back Read/Write Cycle Timing
- •Figure 18.4 Data# Polling Timings (During Embedded Algorithms)
- •Figure 18.5 Toggle Bit Timings (During Embedded Algorithms)
- •17.5 Temporary Sector Unprotect
- •Table 18. Temporary Sector Unprotect
- •Figure 18.1 Temporary Sector Unprotect Timing Diagram
- •Figure 18.3 Sector Protect/Unprotect Timing Diagram
- •17.6 Alternate CE# Controlled Erase/Program Operations
- •Figure 18.1 Alternate CE# Controlled Write Operation Timings
- •18. Erase and Programming Performance
- •19. TSOP and BGA Pin Capacitance
- •19.3 VBN048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 10.0 x 6.0 mm
- •20. Document History Page
- •RYSU
- •RYSU
- •RYSU
- •RYSU
- •RYSU
- •RYSU
- •Sales, Solutions, and Legal Information
- •Worldwide Sales and Design Support
- •Products
- •PSoC® Solutions
- •Cypress Developer Community
- •Technical Support
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S29AL032D |
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18. Erase and Programming Performance |
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Parameter |
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Typ (Note 1) |
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Max (Note 2) |
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Unit |
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Comments |
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Sector Erase Time (Note 7) |
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0.7 |
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10 |
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s |
Excludes 00h programming |
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Chip Erase Time (Note 8) |
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45 |
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s |
prior to erasure (Note 4) |
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Byte Programming Time |
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9 |
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300 |
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µs |
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Word Programming Time |
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11 |
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360 |
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µs |
Excludes system level overhead |
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Accelerated Byte/Word Programming Time |
7 |
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210 |
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µs |
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(Note 5) |
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Chip Programming Time |
Byte Mode |
36 |
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108 |
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s |
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(Note 3) |
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Word Mode |
24 |
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72 |
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s |
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Notes |
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1. |
Typical program and erase times assume the following conditions: 25 C, VCC = 3.0 V, 100,000 cycles, checkerboard data pattern. |
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2. |
Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. |
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Design |
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3. |
The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes pro ram faster than |
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the maximum program times listed. |
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4. |
In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. |
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5. |
System-level overhead is the time required to execute the twoor four-bus-cycle sequence for the program command. See Table 13 for further |
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information on command definitions. |
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New |
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6. |
The device has a minimum erase and program cycle endurance of 100,000 cycles per sector. |
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7. |
At extended temperature range (>+85°C), typical erase time is 1.75 s and maximum erase time is 25 s. |
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8. |
At extended temperature range (>+85°C), typical erase time is 112 s. |
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19. TSOP and BGA Pin Capacitance |
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Parameter Symbol |
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Recommended |
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Test Setup |
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Package |
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Max |
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Unit |
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Parameter Description |
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CIN |
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Input Capacitance |
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VIN = 0 |
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TSOP |
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6 |
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7.5 |
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pF |
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BGA |
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4.2 |
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5.0 |
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pF |
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COUT |
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Output Capacitance |
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VOUT = 0 |
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8.5 |
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12 |
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pF |
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BGA |
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5.4 |
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6.5 |
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pF |
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CIN2 |
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Control Pin Capacitance |
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VIN = 0 |
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7.5 |
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pF |
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BGA |
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3.9 |
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4.7 |
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pF |
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Notes |
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1. |
Sampled, not 100% tested. |
Not |
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2. |
Test conditions TA = 25°C, f = 1.0 MHz.Physical Dimensions |
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Document Number: 002-02003 Rev. *B |
Page 57 of 64 |
S29AL032D
19.1TS040—40-Pin Standard TSOP
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New |
Design |
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for |
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Recommended |
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Dwg rev AA; 10/99 |
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Not |
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Document Number: 002-02003 Rev. *B |
Page 58 of 64 |
S29AL032D
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New |
Design |
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for |
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Recommended |
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Dwg rev AA; 10/99 |
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Not |
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Document Number: 002-02003 Rev. *B |
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Page 59 of 64 |
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S29AL032D
19.2TS 048—48-Pin Standard TSOP
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2X |
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STANDARD PIN OUT (TOP VIEW) |
0.10 |
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2X (N/2 TIPS) |
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2 |
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2X |
0.10 |
0.10 |
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A2 |
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1 |
N |
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REVERSE PIN OUT (TOP VIEW) |
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A |
SEE DETAIL B |
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B |
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3 |
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E |
5 |
1 |
N |
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N |
N |
+1 |
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e |
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2 |
2 |
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D1 |
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9 |
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4 |
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A1 N |
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D |
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Design |
N |
+1 |
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2 |
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2 |
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0.25 |
B |
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C |
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2X (N/2 TIPS) |
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A |
SEATING |
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PLANE |
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B |
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SEE DETAIL A |
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0.08MM (0.0031") |
M |
C A - B S |
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b |
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6 |
7 |
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New |
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WITH PLATING |
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7 |
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(c) |
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c1 |
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Recommended |
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b1 |
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BASE METAL |
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SECTION B-B |
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R |
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(c) |
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e/2 |
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GAUGE PLANE |
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PARALLEL TO |
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q° |
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0.25MM (0.0098") BSC |
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X |
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C |
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SEATING PLANE |
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L |
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X = A OR B |
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DETAIL A |
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DETAIL B |
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NOTES:
Jedec |
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MO-142 (D) DD |
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Symbol |
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MAX |
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A |
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1.20 |
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A1 |
0.05 |
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0.15 |
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A2 |
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1.00 |
1.05 |
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b1 |
0.17 |
0.20 |
0.23 |
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b |
0.17 |
0.22 |
0.27 |
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c1 |
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0.16 |
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c |
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0.21 |
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D19.80 20.00 20.20
D1 18.30 18.40 18.50
E11.90 12.00 12.10
e |
0.50 BASIC |
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L |
0.50 0.60 |
0.70 |
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0 |
0° |
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8˚ |
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R |
0.08 |
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0.20 |
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N |
48 |
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1CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
2PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).
3PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
4TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
5DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15mm (.0059") PER SIDE.
6DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
7THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND 0.25MM (0.0098") FROM THE LEAD TIP.
8LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.
9DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
3355 \ 16-038.10c
* For reference only. BSC is an ANSI standard for Basic Space Centering.
Document Number: 002-02003 Rev. *B |
Page 60 of 64 |
