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S29AL032D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

18. Erase and Programming Performance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

 

 

Typ (Note 1)

 

Max (Note 2)

 

 

Unit

 

 

Comments

 

 

Sector Erase Time (Note 7)

 

 

 

 

0.7

 

 

10

 

 

 

s

Excludes 00h programming

 

Chip Erase Time (Note 8)

 

 

 

 

45

 

 

 

 

 

 

s

prior to erasure (Note 4)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte Programming Time

 

 

 

 

9

 

 

300

 

 

 

µs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Word Programming Time

 

 

 

 

11

 

 

360

 

 

 

µs

Excludes system level overhead

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Accelerated Byte/Word Programming Time

7

 

 

210

 

 

 

µs

 

 

 

 

 

 

(Note 5)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Chip Programming Time

Byte Mode

36

 

 

108

 

 

 

s

 

 

 

 

 

 

 

(Note 3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Word Mode

24

 

 

72

 

 

 

s

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.

Typical program and erase times assume the following conditions: 25 C, VCC = 3.0 V, 100,000 cycles, checkerboard data pattern.

 

 

 

 

 

2.

Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.

 

 

 

 

 

 

Design

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.

The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes pro ram faster than

 

 

 

the maximum program times listed.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4.

In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

 

 

 

 

 

 

 

5.

System-level overhead is the time required to execute the twoor four-bus-cycle sequence for the program command. See Table 13 for further

 

 

 

information on command definitions.

 

 

 

 

 

New

 

 

 

 

 

 

 

 

6.

The device has a minimum erase and program cycle endurance of 100,000 cycles per sector.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7.

At extended temperature range (>+85°C), typical erase time is 1.75 s and maximum erase time is 25 s.

 

 

 

 

 

 

 

 

8.

At extended temperature range (>+85°C), typical erase time is 112 s.

 

 

for

 

 

 

 

 

 

 

 

 

 

 

19. TSOP and BGA Pin Capacitance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter Symbol

 

 

 

 

Recommended

 

Test Setup

 

Package

 

Typ

 

Max

 

Unit

 

 

 

Parameter Description

 

 

 

 

 

 

 

 

CIN

 

 

 

Input Capacitance

 

 

VIN = 0

 

TSOP

 

6

 

7.5

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BGA

 

4.2

 

5.0

 

pF

 

 

COUT

 

 

 

Output Capacitance

 

 

VOUT = 0

 

TSOP

 

8.5

 

12

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BGA

 

5.4

 

6.5

 

pF

 

 

CIN2

 

Control Pin Capacitance

 

 

VIN = 0

 

TSOP

 

7.5

 

9

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BGA

 

3.9

 

4.7

 

pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.

Sampled, not 100% tested.

Not

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.

Test conditions TA = 25°C, f = 1.0 MHz.Physical Dimensions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document Number: 002-02003 Rev. *B

Page 57 of 64

S29AL032D

19.1TS040—40-Pin Standard TSOP

 

 

 

New

Design

 

 

for

 

 

Recommended

 

 

 

 

 

Dwg rev AA; 10/99

 

 

 

 

Not

 

 

 

 

Document Number: 002-02003 Rev. *B

Page 58 of 64

S29AL032D

 

 

 

New

Design

 

 

for

 

 

Recommended

 

 

 

 

 

Dwg rev AA; 10/99

 

 

 

 

Not

 

 

 

 

Document Number: 002-02003 Rev. *B

 

 

Page 59 of 64

S29AL032D

19.2TS 048—48-Pin Standard TSOP

 

 

2X

 

 

 

 

STANDARD PIN OUT (TOP VIEW)

0.10

 

2X (N/2 TIPS)

 

 

 

 

 

 

 

 

 

 

 

 

2

 

2X

0.10

0.10

 

 

 

 

A2

 

 

1

N

 

REVERSE PIN OUT (TOP VIEW)

 

 

 

 

 

 

 

 

A

SEE DETAIL B

 

B

 

 

3

 

 

 

E

5

1

N

 

 

 

 

 

 

N

N

+1

 

e

 

 

2

2

 

 

 

 

 

 

 

D1

5

 

 

 

9

 

 

 

 

 

 

 

 

 

 

4

 

 

 

A1 N

 

 

 

 

 

 

 

 

 

D

 

 

 

 

Design

N

+1

 

 

 

 

 

 

 

 

2

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.25

B

 

 

 

 

 

 

C

 

 

 

 

 

 

 

2X (N/2 TIPS)

 

 

 

 

A

SEATING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLANE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B

 

SEE DETAIL A

 

 

 

0.08MM (0.0031")

M

C A - B S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

b

 

6

7

 

 

 

 

 

 

 

 

 

 

 

New

 

 

WITH PLATING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

(c)

 

 

 

 

c1

 

 

 

 

 

 

 

Recommended

for

 

b1

 

 

BASE METAL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SECTION B-B

 

 

 

 

 

 

 

 

 

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(c)

 

 

 

 

 

 

 

e/2

 

 

 

 

 

 

 

 

GAUGE PLANE

 

 

 

 

 

 

PARALLEL TO

 

 

 

0.25MM (0.0098") BSC

 

 

 

X

 

 

 

 

 

C

 

 

 

 

 

 

 

 

 

SEATING PLANE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

X = A OR B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DETAIL A

 

 

 

 

 

 

DETAIL B

 

 

 

 

 

Not

 

 

 

 

 

 

 

 

 

 

 

NOTES:

Jedec

 

MO-142 (D) DD

Symbol

MIN

NOM

MAX

A

 

 

 

 

 

 

1.20

 

 

 

 

 

 

A1

0.05

 

 

 

0.15

 

 

 

A2

0.95

1.00

1.05

b1

0.17

0.20

0.23

b

0.17

0.22

0.27

c1

0.10

 

 

 

0.16

 

 

 

c

0.10

 

 

 

0.21

 

 

 

D19.80 20.00 20.20

D1 18.30 18.40 18.50

E11.90 12.00 12.10

e

0.50 BASIC

L

0.50 0.60

0.70

0

 

 

 

 

R

0.08

 

 

0.20

 

 

N

48

 

1CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)

2PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).

3PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.

4TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.

5DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15mm (.0059") PER SIDE.

6DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").

7THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND 0.25MM (0.0098") FROM THE LEAD TIP.

8LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.

9DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

3355 \ 16-038.10c

* For reference only. BSC is an ANSI standard for Basic Space Centering.

Document Number: 002-02003 Rev. *B

Page 60 of 64

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