S29AL032D
Figure 17.4 BYTE# Timings for Write Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE# |
tSET |
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(tAS) |
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tHOLD (tAH) |
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Note
Refer to the Erase/Program Operations table for tAS and tAH specifications.
17.4Erase/Program Operations
Table 18. Erase/Program Operations
Parameter
JEDEC Std.
tAVAV tWC
tAVWL tAS
tWLAX tAH
tDVWH tDS
tWHDX tDH
tOES
tGHWL tGHWL
tELWL tCS
tWHEH tCH
tWLWH tWP
tWHWL tWPH
tSR/W
tWHWH1 tWHWH1
tWHWH1 tWHWH1
tWHWH2 tWHWH2
tVCS
tRB
tBUSY
Description
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Hold Time
Data SetupRecommendedTime
Output Enable Setup Time
Read Recovery Time Before Write (OE# High to WE# Low)
CE# Setup Time
CE# Hold Time
Write Pulse Width
Write Pulse Width High
LatencyNotBe ween Read and Write Operations
Programming Operation (Note 2)
Accelerated Programming Operation, Word or
Sector Erase Operation (Note 2)
for |
New |
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Byte
Word
Byte (Note 2)
VCC Setup Time (Note 1)
Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
Notes
1.Not 100% tested.
2.See Erase and Programming Performance on page 57 for more information.
Design |
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Speed Options |
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Unit |
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70 |
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90 |
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Min |
70 |
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90 |
ns |
Min |
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0 |
ns |
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Min |
45 |
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ns |
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45 |
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Min |
35 |
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45 |
ns |
Min |
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0 |
ns |
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Min |
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0 |
ns |
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Min |
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0 |
ns |
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Min |
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0 |
ns |
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Min |
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0 |
ns |
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Min |
35 |
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ns |
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35 |
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Min |
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30 |
ns |
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Min |
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20 |
ns |
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9 |
µs |
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11 |
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7 |
µs |
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Typ |
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0.7 |
sec |
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Min |
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50 |
µs |
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Min |
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0 |
ns |
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Max |
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90 |
ns |
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Figure 18.1 Program Operation Timings
Notes
1.PA = program address, PD = program data, DOUT is the true data at the program address.
2.Illustration shows device in word mode.
Document Number: 002-02003 Rev. *B |
Page 50 of 64 |
S29AL032D
Program Command Sequence (last two cycles) |
Read Status Data (last two cycles) |
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tWC |
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tAS |
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Addresses |
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555h |
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PA |
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PA |
PA |
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tAH |
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CE# |
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tCH |
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OE# |
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tWP |
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tWHWH1 |
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WE# |
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tWPH |
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tCS |
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tDS |
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tDH |
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Data |
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A0h |
PD |
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Status |
DOUT |
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tBUSY |
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tRB |
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RY/BY# |
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tVCS |
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VCC |
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Figure 18.2 |
Chip/Sector Erase Operation Timings |
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Erase Command Sequence (last two cycles) |
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Read Status Data |
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tWC |
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tAS |
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Addresses |
2AAh |
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SA |
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VA |
VA |
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555h for chip erase |
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tAH |
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CE# |
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OE# |
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tCH |
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t |
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RecommendedWP |
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WE# |
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tWPH |
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tWHWH2 |
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tCS |
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Not |
tDS |
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tDH |
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Data |
55h |
30h |
In |
Complete |
Progress |
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10 for Chip Erase |
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tBUSY |
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tRB |
RY/BY#
tVCS 
VCC
Notes
1.SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 37).
2.Illustration shows device in word mode.
Document Number: 002-02003 Rev. *B |
Page 51 of 64 |
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S29AL032D |
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Figure 18.3 Back to Back Read/Write Cycle Timing |
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tWC |
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tRC |
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Addresses |
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PA |
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RA |
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PA |
PA |
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tAH |
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tACC |
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tCPH |
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tCE |
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CE# |
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tOE |
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tCP |
OE# |
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tSR/W |
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tGHWL |
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WE# |
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tWP |
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tDF |
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tWDH |
tDS |
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tDH |
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tOH |
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Data |
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Valid In |
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Valid Out |
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Valid In |
Valid Out |
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Design |
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Figure 18.4 Data# Polling Timings (During Embedded Algorithms) |
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Addresses |
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tRC |
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New |
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VA |
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VA |
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VA |
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tACC |
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for |
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CE# |
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tCE |
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tCH |
tOE |
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OE# |
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tOEH |
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tDF |
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WE# |
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tOH |
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DQ7 |
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High Z |
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Complement |
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Complement |
True |
Valid Data |
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DQ0–DQ6 |
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Recommended |
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High Z |
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Status Data |
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Status Data |
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True |
Valid Data |
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tBUSY |
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Not |
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RY/BY# |
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Note
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Document Number: 002-02003 Rev. *B |
Page 52 of 64 |