S29AL032D

Figure 16.1 Input Waveforms and Measurement Levels

VCC

0.5 VCC

0.5 VCC Output

Input

Measurement Level

0.0 V

17. AC Characteristics

Parameter

Description

Speed Options

JEDEC

Std

Test Setup

70

90

Unit

tAVAV

tRC

Read Cycle Time (Note 1)

Min

70

90

ns

tAVQV

tACC

Address to Output Delay

CE# = VIL

Max

70

90

ns

OE# = VIL

tELQV

tCE

Chip Enable to Output Delay

OE# = VIL

Max

70

90

ns

tGLQV

tOE

Output Enable to Output Delay

Max

30

35

ns

Design

tEHQZ

tDF

Chip Enable to Output High Z (Note 1)

Max

16

ns

tGHQZ

tDF

Output Enable to Output High Z (Note 1)

Max

16

ns

tSR/W

Latency Between Read and Write Operations

New

Min

20

ns

tOEH

Output Enable

Read

Min

0

ns

Hold Time (Note 1)

Toggle and Data# Polling

for

Min

10

ns

tAXQX

tOH

Output Hold Time From Addresses, CE# or OE#, Whichever

Min

0

ns

Occurs First (Note 1)

Notes

1. Not 100% tested.

2. See Figure 16.1 on page 46 and Table 17 on page 46 for test specifications.

Figure 17.1 Read Operations Timings

tRC

Not

Recommended

Addresses

Addresses Stable

tACC

CE#

tDF

OE#

tSR/W

tOE

tOEH

WE#

tCE

tOH

HIGH Z

HIGH Z

Outputs

Output Valid

RESET#

RY/BY#

0 V

Document Number: 002-02003 Rev. *B

Page 47 of 64