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Файл:ПЛИС / FPGA Sixth Flash / S29AL032D.pdf
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- •Distinctive Characteristics
- •General Description
- •S29AL032D Features
- •1. Product Selector Guide
- •2. Block Diagram
- •3. Connection Diagrams
- •Figure 3.1 40-pin Standard TSOP
- •3.1 FBGA Package for Model 00 Only
- •Figure 3.3 Model 00 48-ball FBGA (Top View, Balls Facing Down)
- •3.2 FBGA Package for Models 03, 04 Only
- •Figure 3.4 Models 03, 04 48-ball FBGA (Top View, Balls Facing Down)
- •3.3 Special Handling Instructions
- •4. Pin Configuration
- •5. Logic Symbols
- •6. Ordering Information
- •6.1 S29AL032D Standard Products
- •6.2 Valid Combinations
- •7. Device Bus Operations
- •Table 8. S29AL032D Device Bus Operations
- •7.1 Word/Byte Configuration (Models 03, 04 Only)
- •7.2 Requirements for Reading Array Data
- •7.4 Program and Erase Operation Status
- •7.5 Accelerated Program Operation
- •7.6 Standby Mode
- •7.7 Automatic Sleep Mode
- •7.8 RESET#: Hardware Reset Pin
- •7.9 Output Disable Mode
- •7.10 Sector Addresss Tables
- •Table 8. Model 00 Sector Addresses (Sheet 1 of 2)
- •Table 9. Model 00 Secured Silicon Sector Addresses
- •Table 10. Model 03 Sector Addresses (Sheet 1 of 2)
- •Table 11. Model 03 Secured Silicon Sector Addresses
- •Table 12. Model 04 Sector Addresses (Sheet 1 of 2)
- •Table 13. Model 04 Secured Silicon Sector Addresses
- •7.11 Autoselect Mode
- •Table 8. S29AL032D Autoselect Codes (High Voltage Method)
- •7.12 Sector Protection/Unprotection
- •Table 8. Sector Block Addresses for Protection/Unprotection — Model 00
- •Table 9. Sector Block Addresses for Protection/Unprotection — Model 03 (Sheet 1 of 2)
- •7.13 Write Protect (WP#) — Models 03, 04 Only
- •7.14 Temporary Sector Unprotect
- •8. Secured Silicon Sector Flash Memory Region
- •Figure 8.1 Secured Silicon Sector Protect Verify
- •9. Hardware Data Protection
- •9.1 Low VCC Write Inhibit
- •9.2 Write Pulse “Glitch” Protection
- •9.3 Logical Inhibit
- •10. Common Flash Memory Interface (CFI)
- •Table 11. CFI Query Identification String
- •Table 12. System Interface String
- •Table 13. Device Geometry Definition
- •11. Command Definitions
- •11.1 Reading Array Data
- •11.2 Reset Command
- •11.3 Autoselect Command Sequence
- •11.6 Unlock Bypass Command Sequence
- •Figure 11.1 Program Operation
- •11.7 Chip Erase Command Sequence
- •11.8 Sector Erase Command Sequence
- •Figure 11.2 Erase Operation
- •11.10 Command Definitions Table
- •Table 12. S29AL032D Command Definitions — Model 00
- •12. Write Operation Status
- •12.1 DQ7: Data# Polling
- •Figure 12.1 Data# Polling Algorithm
- •12.2 RY/BY#: Ready/Busy#
- •12.3 DQ6: Toggle Bit I
- •12.4 DQ2: Toggle Bit II
- •12.5 Reading Toggle Bits DQ6/DQ2
- •Figure 12.2 Toggle Bit Algorithm
- •12.6 DQ5: Exceeded Timing Limits
- •12.7 DQ3: Sector Erase Timer
- •Table 13. Write Operation Status
- •13. Absolute Maximum Ratings
- •Table 14. Absolute Maximum Ratings
- •14. Operating Ranges
- •Table 15. Operating Ranges
- •15. DC Characteristics
- •Table 16. DC Characteristics, CMOS Compatible
- •15.1 Zero Power Flash
- •Figure 15.2 Typical ICC1 vs. Frequency
- •16. Test Conditions
- •16.1 Key to Switching Waveforms
- •Figure 16.1 Input Waveforms and Measurement Levels
- •17. AC Characteristics
- •17.1 Read Operations
- •Figure 17.1 Read Operations Timings
- •17.2 Hardware Reset (RESET#)
- •17.3 Word/Byte Configuration (BYTE#) (Models 03, 04 Only)
- •Figure 17.3 BYTE# Timings for Read Operations
- •Figure 17.4 BYTE# Timings for Write Operations
- •17.4 Erase/Program Operations
- •Table 18. Erase/Program Operations
- •Figure 18.1 Program Operation Timings
- •Figure 18.3 Back to Back Read/Write Cycle Timing
- •Figure 18.4 Data# Polling Timings (During Embedded Algorithms)
- •Figure 18.5 Toggle Bit Timings (During Embedded Algorithms)
- •17.5 Temporary Sector Unprotect
- •Table 18. Temporary Sector Unprotect
- •Figure 18.1 Temporary Sector Unprotect Timing Diagram
- •Figure 18.3 Sector Protect/Unprotect Timing Diagram
- •17.6 Alternate CE# Controlled Erase/Program Operations
- •Figure 18.1 Alternate CE# Controlled Write Operation Timings
- •18. Erase and Programming Performance
- •19. TSOP and BGA Pin Capacitance
- •19.3 VBN048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 10.0 x 6.0 mm
- •20. Document History Page
- •RYSU
- •RYSU
- •RYSU
- •RYSU
- •RYSU
- •RYSU
- •Sales, Solutions, and Legal Information
- •Worldwide Sales and Design Support
- •Products
- •PSoC® Solutions
- •Cypress Developer Community
- •Technical Support

S29AL032D
3.1FBGA Package for Model 00 Only
Figure 3.3 Model 00 48-ball FBGA (Top View, Balls Facing Down)
A6 |
|
B6 |
C6 |
D6 |
|
E6 |
A14 |
|
A13 |
A15 |
A16 |
|
A17 |
A5 |
|
B5 |
C5 |
D5 |
|
E5 |
A9 |
|
A8 |
A11 |
A12 |
|
A19 |
A4 |
|
B4 |
C4 |
D4 |
|
E4 |
WE# |
RESET# |
NC |
NC |
DQ5 |
||
A3 |
|
B3 |
C3 |
D3 |
|
E3 |
RY/BY# |
|
ACC |
NC |
NC |
DQ2 |
|
A2 |
|
B2 |
C2 |
D2 |
|
E2 |
A7 |
|
A18 |
A6 |
A5 |
|
for |
|
DQ0 |
|||||
A1 |
|
Recommended |
E1 |
|||
|
B1 |
C1 |
D1 |
|
||
A3 |
|
A4 |
A2 |
A1 |
|
A0 |
Not |
|
|
|
|
|
F6
NC
F5
A10
F4
NC
F3
NewDQ3
F2
NC
F1
CE#
G6 |
H6 |
A20 |
VSS |
G5 |
H5 |
DQ6 |
DQ7 |
Design |
|
G4 |
H4 |
VCC |
DQ4 |
G3 |
H3 |
VCC |
A21 |
G2 |
H2 |
NC |
DQ1 |
G1 |
H1 |
OE# |
VSS |
Document Number: 002-02003 Rev. *B |
Page 6 of 64 |
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