Development Board Components
The switches connect to an FPGA general-purpose I/O pin with a pull-up resistor through the Schmitt Trigger outputs, KEY0, …, KEY3. Each I/O pin senses a logic level 0 when the corresponding switch is pressed.
The debounced outputs enable users to use the push buttons as clock or reset inputs for a circuit.
Push Button Switch Schematic
Figure 2–12 shows a schematic diagram of the push button switches.
Figure 2–12. Push Button Switch Schematic Diagram
Push Button Switch Pin List
Table 2–10 lists the FPGA pins assigned to the push button switches.
Table 2–10. Push Button Switch FPGA Pin Connections
Switch |
FPGA Pin |
Description |
|
|
|
KEY[0] |
PIN_R22 |
Pushbutton[0] |
|
|
|
KEY[1] |
PIN_R21 |
Pushbutton[1] |
|
|
|
KEY[2] |
PIN_T22 |
Pushbutton[2] |
|
|
|
KEY[3] |
PIN_T21 |
Pushbutton[3] |
|
|
|
Toggle Switches
The development board provides ten sliding toggle switches, SW0–SW9, located at the bottom left on the development board below the red LEDs, LEDR0-LEDR9 (Figure 2–13). Not debounced, these switches provide level-sensitive data inputs to a circuit. Each switch
Altera Corporation |
Reference Manual |
2–17 |
October 2006 |
Cyclone II FPGA Starter Development Board |
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Development Board Components
connects directly to a pin on the FPGA. In the DOWN or OFF position (closest to the edge of the board), a switch provides a LOW logic level (0 volts) to the FPGA. In the UP position a switch provides a HIGH logic level (3.3 volts).
Figure 2–13. Toggle Switches SW0–SW9 and Red LEDs LEDR0-LEDR9
Toggle Switch Schematic
Figure 2–14 shows a schematic diagram of the toggle switches.
Figure 2–14. Toggle Switch Schematic Diagram
2–18 |
Reference Manual |
Altera Corporation |
Cyclone II FPGA Starter Development Board |
October 2006 |
|