The op-code is decoded in this stage. When present, the instruction address is used for address computation, whilst the immediate operand is forwarded to the execution stage.

Long/unaligned instructions

For long instructions (i.e. 5-bytes instructions), the fetch may need 2 program memory accesses to be completed. In this case, the decoding stage (after decoding the op-code part), is stalled waiting for the fetch stage to complete the 2nd fetch.

In case of shorter instructions, this may also happen when they cross a 32-bit boundary.

Indirect addressing

For indirect addressing, the CPU is stalled in this stage to read the pointer from the data memory (i.e. RAM). The number of cycles during which the CPU is stalled depends on the pointer size (short, long or extended addressing mode).

5.1.3Execution stage

In the execution stage, the operation is executed and the result is stored in the accumulator, index register or RAM.

5.2Data memory conflicts

3 types of operations perform accesses to the data memory:

●Effective address computation in case of indirect addressing

●Data read: source operand

●Data write: destination for store or read-modify-write operations

In case of simultaneous accesses to the same memory area both in execution stage (write) and decoding stage (read), the decode stage is stalled till the execution stage releases the resource.