PM0044 |
STM8 instruction set |
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7 STM8 instruction set
7.1Introduction
This chapter describes all the STM8 instructions. There are 96 and they are described in alphabetical order. However, they can be classified in 13 main groups as follows:
Table 41. Instruction groups
Load and |
LD |
LDF |
CLR |
MOV |
EXG |
LDW |
CLRW |
EXGW |
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Transfer |
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Stack |
PUSH |
POP |
PUSH |
POPW |
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operation |
W |
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Increment/ |
INC |
DEC |
INCW |
DECW |
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Decrement |
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Compare and |
CP |
TNZ |
BCP |
CPW |
TNZW |
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Tests |
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Logical |
AND |
OR |
XOR |
CPL |
CPLW |
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operations |
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Bit Operation |
BSET |
BRES |
BCPL |
BCCM |
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Conditional Bit |
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Test and |
BTJT |
BTJF |
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Branch |
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Arithmetic |
NEG |
ADC |
ADD |
SUB |
SBC |
MUL |
DIV |
DIVW |
NEGW |
ADDW |
SUBW |
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operations |
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Shift and |
SLL |
SRL |
SRA |
RLC |
RRC |
SWAP |
SLLW |
SRLW |
SRAW |
RLCW |
RRCW |
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Rotates |
SWAP |
RLWA |
RRWA |
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Unconditional |
JRA |
JRT |
JRF |
JP |
JPF |
CALL |
CALLR |
CALLF |
RET |
RETF |
NOP |
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Jump or Call |
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Conditional |
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Branch/ |
JRxx |
WFE |
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Execution |
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Interrupt |
TRAP |
WFI |
HALT |
IRET |
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management |
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Condition |
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Code Flag |
SIM |
RIM |
SCF |
RCF |
CCF |
RVF |
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modification |
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Breakpoint/ |
BREAK |
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software break |
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The instructions are described with one to five bytes.
PC-1 End of previous instruction
PC Op-code
PC+1..4 Additional word (0 to 4) according to the number of bytes required to compute the effective address(es)
Doc ID 13590 Rev 3 |
61/162 |
STM8 instruction set |
PM0044 |
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Using a pre-code (two-byte op-codes)
In order to extend the number of available op-codes for an 8-bit CPU (256 op-codes), four different pre-code bytes are defined. These pre-codes modify the meaning of the instruction they precede.
The whole instruction becomes:
PC-1 End of previous instruction
PC Pre-code
PC+1 Op-code
PC+2 Additional word (0 to 3) according to the number of bytes required to compute the effective address
These pre-bytes are: |
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0x90 |
= PDY |
Replaces an X based instruction using immediate, direct, indexed or |
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inherent addressing mode by a Y one. |
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It also provides read/modify/write instructions using Y indexed |
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addressing mode with long offset and two bit handling instructions |
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(BCPL and BCCM) |
0x92 |
= PIX |
Replaces an instruction using direct, direct bit, or direct relative |
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addressing mode to an instruction using the corresponding indirect |
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addressing mode. |
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It also changes an instruction using X indexed addressing mode to |
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an instruction using indirect X indexed addressing mode. |
0x91 |
= PIY |
Replace an instruction using indirect X indexed addressing mode by |
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a Y one. |
0x72 |
= PWSP |
Provide long addressing mode for bit handling and read/modify/write |
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instructions. |
It also provides indirect addressing mode with two byte pointer for read/modify/write and register/memory instructions.
Finally it provides stack pointer indexed addressing mode on register/memory instructions.
62/162 |
Doc ID 13590 Rev 3 |