PM0044 |
Pipelined execution |
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5.4.5Pipeline with 1 wait state
In the example given in Table 14, performing the fetch takes 2 cycles, and there is no overlap between the 2 fetch cycles.
If the instruction is decoded/executed during the last 2 fetch cycles, then the wait state is transparent compared to the no-wait state execution.
Table 14. |
Pipeline with 1 wait state |
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Address |
Instruction |
Decode |
Execute |
lgth |
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Time (cycle) |
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cycles |
cycles |
1 |
2 |
3 |
4 |
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5 |
6 |
7 |
8 |
9 |
10 |
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0xC000 |
NEG A |
1 |
1 |
1 |
MS |
F1 |
D |
E |
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0xC001 |
DEC ($10, X) |
1 |
1 |
3 |
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D |
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E |
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0xC004 |
LDW X, #20 |
1 |
1 |
3 |
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MS |
F2 |
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D |
E |
E |
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0xC007 |
LD (X), A |
1 |
1 |
1 |
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D |
D |
E |
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0xC008 |
INC A |
1 |
1 |
1 |
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MS |
F3 |
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D |
E |
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0xC009 |
NEG ($5A, Y) |
1 |
1 |
1 |
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D |
E |
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Table 15. Legend
Symbol/Color |
Definition |
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F |
Fetch |
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D |
Decode stalled |
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D |
Decode |
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MS |
Memory stalled |
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E |
Execute |
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Doc ID 13590 Rev 3 |
29/162 |