5.4.2Optimize pipeline example – execution from RAM

In the example shown in Table 8, the RAM is accessed through an 8-bit bus. As a result, 12 cycles are required to fill the 96-bit pre-fetch buffer. Every 4 cycles, one word is loaded and stored in Fx. The decoding of the first word instruction can start only when the Fx word is filled. This occurs for example till the 4th cycle, and the first instruction (NEG A) can be decoded only at the 5th cycle.

In case of read/write access to the RAM, the fetch is stalled. This occurs during the 6th cycle since RAM address 10 is read during the decode stage of XOR A, $10.