Digital-Logic
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NAND gate implementation of the “sum-of-product” logic functions
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F = AB + AC |
NAND gates are faster than ANDs and |
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ORs in most technologies |
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X = ( X ) |
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© Emil M. Petriu
ADDING BINARY NUMBERS
Adding two bits:
Truth table
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Carry Sum |
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Sum = A + B
Carry = A . B
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The binary |
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number 10 is |
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equivalent to |
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the decimal 2 |
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(over)
A
Sum
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Half-Adder |
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circuit |
Carry |
© Emil M. Petriu
Adding multi-bit numbers:
108D + |
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1 1 0 1 1 0 0 + |
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A7 A6 A5 A4 A3 A2 A1 A0 + |
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90D |
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1 0 1 1 0 1 0 |
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B7 B6 B5 B4 B3 |
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198D |
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1 1 |
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Sum |
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Carry Out
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A4 B4
A B
CO CI
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Carry In = 0
S7 |
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S4 |
S3 |
S2 |
S1 |
S0 |
© Emil M. Petriu
Full Adder
Bits of the same rank of the two numbers
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Sum
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B CI |
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CI |
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B. CI A . CI
S = A . B . CI + A . B . CI + A . B . CI + A . B . CI C = A . B + B . CI + A . CI
© Emil M. Petriu
HEX-TO-7 SEGMENT DECODER
This examples illustrates how a practical problem is analyzed in order to generate truth tables,and then how truth table-defined functions are mapped on Karnaugh maps.
B3 B2 B1 B0
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Four-bit |
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S1 |
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7-segment display to allow |
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“machine” |
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the user see the natural |
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representation |
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representation of the |
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of the hex |
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hex digits. |
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digits |
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Binary outputs; when |
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such a signal is = 1 then |
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the corresponding segment |
in the 7-segment display |
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is on (you see it), when the |
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7 SEGMENT |
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signal is = 0 then the |
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segment is off (you can’t |
HEX |
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see it). |
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B3 B2 B1 B0 |
The four-bit representation |
of the hex digits |
“Natural” (i.e.as humans write) |
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representation of the “hex” digits. |
© Emil M. Petriu |
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B3 B2 B1 B0
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S1 |
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We are developing ad- hoc”binary-hex logic” expressions used just for our convenience in the problem analysis process. Each expression will enumerate only those hex digits when the specific display-segment is “on”: 
S1 = 0+2 +3+5+6+7+8+9+A+C+E+F S2 = 0+1+2+3+4+7+8+9+A+D
S3 = 0+1+3+4+5+6+7+8+9+A+B+D |
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S4 = 0+2+3+5+6+8+9+B+C+D+E |
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S4
S5 = 0+2+6+8+A+B+C+D+E+F
S6 = 0+4+5+6+8+9+A+B+C+E+F
S7 = 2+3+4+5+6+8+9+A+B+D+E+F
© Emil M. Petriu
Hex-to-7 segment
B3 B2 B1 B0
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S1 = 0+2 +3+5+6+7+8+9+A+C+E+F S2 = 0+1+2+3+4+7+8+9+A+D
S3 = 0+1+3+4+5+6+7+8+9+A+B+D S4 = 0+2+3+5+6+8+9+B+C+D+E S5 = 0+2+6+8+A+B+C+D+E+F
S6 = 0+4+5+6+8+9+A+B+C+E+F S7 = 2+3+4+5+6+8+9+A+B+D+E+F
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As we are using ad-hoc “binary-hex logic” equations, (i.e. binary S… outputs as functions of hex variables) it will useful in this case to have
hex-labeled Karnaugh map, instead of the usual 2-D (i.e. two dimensional) binary labeled K maps. This will allow for a more convenient mapping of the “binary-hex” logic equations onto the K-maps.
© Emil M. Petriu
Hex-to-7 segment
Mapping the ad-hoc “binary-hex |
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B1 B0 |
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logic” equations onto Karnaugh maps: |
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S1 = 0+2 +3+5+6+7+8+9+A+C+E+F |
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S2 = 0+1+2+3+4+7+8+9+A+D |
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S3 = 0+1+3+4+5+6+7+8+9+A+B+D |
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S4 = 0+2+3+5+6+8+9+B+C+D+E |
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Hex-to-7 segment |
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B3 B2 |
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B1 B0 |
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01 11 |
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D |
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S5 = 0+2+6+8+A+B+C+D+E+F |
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S6 = 0+4+5+6+8+9+A+B+C+E+F |
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S7 = 2+3+4+5+6+8+9+A+B+D+E+F |
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© Emil M. Petriu
SYSTEMS of LOGIC FUNCTIONS |
2- bit Comparator |
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A1 A0 |
B1 B0 |
F1 |
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F2 |
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(0) |
0 |
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1 |
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(1) |
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(2) |
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(4) |
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(5) |
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(6) |
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(7) |
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(8) |
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(9) |
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(10) |
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(11) |
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(12) |
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1 |
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0 |
(13) |
1 |
1 |
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0 |
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0 |
(14) |
1 |
1 |
1 |
0 |
0 |
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1 |
0 |
(15) |
1 |
1 |
1 |
1 |
1 |
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0 |
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Compare two 2-bit numbers:
A=B |
F1 = Σ (0,5,10,15) |
A>B 
F2 = Σ (4,8,9,12,13,14)
A<B |
F3 = Σ (1,2,3,6,7,11) |
© Emil M. Petriu