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Микропроцессорная техника Сторожок / Datasheet.hk_dspic33fj32mc204_1234824

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dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

FIGURE 23-13: QEI MODULE INDEX PULSE TIMING CHARACTERISTICS

QEA (input)

QEB (input)

Ungated

Index

								TQ50
TQ51

Index Internal

TQ55

Position

Counter Reset

TABLE 23-31: QEI INDEX PULSE TIMING REQUIREMENTS

			Standard Operating Conditions: 3.0V to 3.6V
AC CHARACTERISTICS			(unless otherwise stated)
AC CHARACTERISTICS			Operating temperature		-40°C ≤ TA ≤ +85°C for Industrial
			Operating temperature		-40°C ≤ TA ≤ +85°C for Industrial
					-40°C ≤ TA ≤ +125°C for Extended
Param	Symbol	Characteristic(1)		Min		Max	Units	Conditions
No.	Symbol	Characteristic(1)		Min		Max	Units	Conditions
No.

TQ50	TqIL	Filter Time to Recognize Low,		3 * N * TCY		—	ns	N = 1, 2, 4, 16, 32, 64,
		with Digital Filter						128 and 256 (Note 2)
TQ51	TqiH	Filter Time to Recognize High,		3 * N * TCY		—	ns	N = 1, 2, 4, 16, 32, 64,
		with Digital Filter						128 and 256 (Note 2)
TQ55	Tqidxr	Index Pulse Recognized to Position		3 TCY		—	ns	—
		Counter Reset (ungated index)
Note 1:	These parameters are characterized but not tested in manufacturing.

2:Alignment of index pulses to QEA and QEB is shown for position counter Reset timing only. Shown for forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but index pulse recognition occurs on falling edge.

♥ 2007 Microchip Technology Inc.

Preliminary

DS70283B-page 259

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

FIGURE 23-14: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS

SCKx (CKP = 0)

SP11

SP10

SP21

SP20

SCKx

(CKP = 1)

SP35

SP20

SP21

Bit 14 - - - - - -1

MSb

LSb

SDOx

SP31

SP30

SDIx

LSb In

MSb In

Bit 14 - - - -1

SP40

SP41

Note: Refer to Figure 23-1 for load conditions.

TABLE 23-32: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS

			Standard Operating Conditions: 3.0V to 3.6V
AC CHARACTERISTICS			(unless otherwise stated)
AC CHARACTERISTICS			Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
			Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
					-40°C ≤ TA ≤ +125°C for Extended
Param	Symbol	Characteristic(1)	Min	Typ(2)	Max	Units	Conditions
No.	Symbol	Characteristic(1)	Min	Typ(2)	Max	Units	Conditions
No.

SP10	TscL	SCKx Output Low Time	TCY/2	—	—	ns	See Note 3
SP11	TscH	SCKx Output High Time	TCY/2	—	—	ns	See Note 3
SP20	TscF	SCKx Output Fall Time	—	—	—	ns	See parameter D032
							and Note 4
SP21	TscR	SCKx Output Rise Time	—	—	—	ns	See parameter D031
							and Note 4
SP30	TdoF	SDOx Data Output Fall Time	—	—	—	ns	See parameter D032
							and Note 4
SP31	TdoR	SDOx Data Output Rise Time	—	—	—	ns	See parameter D031
							and Note 4
SP35	TscH2doV,	SDOx Data Output Valid after	—	6	20	ns	—
	TscL2doV	SCKx Edge
SP40	TdiV2scH,	Setup Time of SDIx Data Input	23	—	—	ns	—
	TdiV2scL	to SCKx Edge
SP41	TscH2diL,	Hold Time of SDIx Data Input	30	—	—	ns	—
	TscL2diL	to SCKx Edge
Note 1:	These parameters are characterized but not tested in manufacturing.

2:Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3:The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification.

4:Assumes 50 pF load on all SPIx pins.

DS70283B-page 260

Preliminary

♥ 2007 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

FIGURE 23-15: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS

SP36

SCKX (CKP = 0)

SP11

SP10

SP21

SP20

SCKX

(CKP = 1)

SP35

SP20

SP21

SDOX

MSb

Bit 14 - - - - - -1

LSb

SP40

SP30,SP31

SDIX

MSb In

Bit 14 - - - -1

LSb In

SP41

Note: Refer to Figure 23-1 for load conditions.

TABLE 23-33: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

			Standard Operating Conditions: 3.0V to 3.6V
AC CHARACTERISTICS			(unless otherwise stated)
AC CHARACTERISTICS			Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
			Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
					-40°C ≤ TA ≤ +125°C for Extended
Param	Symbol	Characteristic(1)	Min	Typ(2)	Max	Units	Conditions
No.	Symbol	Characteristic(1)	Min	Typ(2)	Max	Units	Conditions
No.

SP10	TscL	SCKx Output Low Time	TCY/2	—	—	ns	See Note 3
SP11	TscH	SCKx Output High Time	TCY/2	—	—	ns	See Note 3
SP20	TscF	SCKx Output Fall Time	—	—	—	ns	See parameter D032
							and Note 4
SP21	TscR	SCKx Output Rise Time	—	—	—	ns	See parameter D031
							and Note 4
SP30	TdoF	SDOx Data Output Fall Time	—	—	—	ns	See parameter D032
							and Note 4
SP31	TdoR	SDOx Data Output Rise Time	—	—	—	ns	See parameter D031
							and Note 4
SP35	TscH2doV,	SDOx Data Output Valid after	—	6	20	ns	—
	TscL2doV	SCKx Edge
SP36	TdoV2sc,	SDOx Data Output Setup to	30	—	—	ns	—
	TdoV2scL	First SCKx Edge
SP40	TdiV2scH,	Setup Time of SDIx Data	23	—	—	ns	—
	TdiV2scL	Input to SCKx Edge
SP41	TscH2diL,	Hold Time of SDIx Data Input	30	—	—	ns	—
	TscL2diL	to SCKx Edge
Note 1:	These parameters are characterized but not tested in manufacturing.

2:Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3:The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this specification.

4:Assumes 50 pF load on all SPIx pins.

♥ 2007 Microchip Technology Inc.

Preliminary

DS70283B-page 261

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

FIGURE 23-16: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS

SSX

SP50

SP52

SCKX

(CKP = 0)

SP71

SP70

SP73

SP72

SCKX

(CKP = 1)

SP35

SP72

SP73

SDOX

MSb

Bit 14 - - - - - -1

LSb

SP51

SP30,SP31

SDIX

MSb In

Bit 14 - - - -1

LSb In

SP41

SP40

Note: Refer to Figure 23-1 for load conditions.

TABLE 23-34: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

AC CHARACTERISTICS

(unless otherwise stated)

Operating temperature

-40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

Characteristic(1)

Min

Typ(2)

Max

Units

Conditions

No.

SP70

TscL

SCKx Input Low Time

—

SP71

TscH

SCKx Input High Time

—

SP72

TscF

SCKx Input Fall Time

—

See Note 3

SP73

TscR

SCKx Input Rise Time

—

See Note 3

SP30

TdoF

SDOx Data Output Fall Time

—

See parameter D032

and Note 3

SP31

TdoR

SDOx Data Output Rise Time

—

See parameter D031

and Note 3

SP35

TscH2doV,

SDOx Data Output Valid after

—

TscL2doV

SCKx Edge

SP40

TdiV2scH,

Setup Time of SDIx Data Input

—

TdiV2scL

to SCKx Edge

SP41

TscH2diL,

Hold Time of SDIx Data Input to

—

TscL2diL

SCKx Edge

SP50

TssL2scH,

↓ to SCKx ↑ or SCKx Input

120

—

SSx

TssL2scL

SP51

TssH2doZ

↑ to SDOx Output

—

See Note 3

SSx

High-Impedance

SP52

TscH2ssH

after SCKx Edge

1.5 TCY +40

—

SSx

TscL2ssH

Note 1:

These parameters are characterized but not tested in manufacturing.

2:Data in “Typ” column is at 5V, 25°C unless otherwise stated.

3:Assumes 50 pF load on all SPIx pins.

DS70283B-page 262

Preliminary

♥ 2007 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

FIGURE 23-17: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS

SSx	SP60
SSx
	SP50			SP52
	SP50
SCKx
(CKP = 0)
	SP71	SP70	SP73	SP72
SCKx
(CKP = 1)		SP35
		SP35
		SP52	SP72	SP73
		SP52
SDOx	MSb	Bit 14 - - - - - -1	LSb
		SP30,SP31		SP51
SDIx	MSb In	Bit 14 - - - -1	LSb In
	MSb In	Bit 14 - - - -1	LSb In
	SP41
	SP40
Note: Refer to Figure 23-1 for load conditions.

♥ 2007 Microchip Technology Inc.

Preliminary

DS70283B-page 263

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

TABLE 23-35: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS

					Standard Operating Conditions: 3.0V to 3.6V
AC CHARACTERISTICS					(unless otherwise stated)
AC CHARACTERISTICS					Operating temperature		-40°C ≤ TA ≤ +85°C for Industrial
					Operating temperature		-40°C ≤ TA ≤ +85°C for Industrial
							-40°C ≤ TA ≤ +125°C for Extended
Param	Symbol			Characteristic(1)	Min	Typ(2)	Max	Units	Conditions
No.	Symbol			Characteristic(1)	Min	Typ(2)	Max	Units	Conditions
No.

SP70	TscL	SCKx Input Low Time			30	—	—	ns	—
SP71	TscH	SCKx Input High Time			30	—	—	ns	—
SP72	TscF		SCKx Input Fall Time		—	10	25	ns	See Note 3
SP73	TscR		SCKx Input Rise Time		—	10	25	ns	See Note 3
SP30	TdoF		SDOx Data Output Fall Time		—	—	—	ns	See parameter
									D032 and Note 3
SP31	TdoR		SDOx Data Output Rise Time		—	—	—	ns	See parameter
									D031 and Note 3
SP35	TscH2doV,		SDOx Data Output Valid after		—	—	30	ns	—
	TscL2doV		SCKx Edge
SP40	TdiV2scH,		Setup Time of SDIx Data Input		20	—	—	ns	—
	TdiV2scL		to SCKx Edge
SP41	TscH2diL,		Hold Time of SDIx Data Input		20	—	—	ns	—
	TscL2diL		to SCKx Edge
SP50	TssL2scH,			↓ to SCKx ↓ or SCKx ↑	120	—	—	ns	—
SP50	TssL2scH,		SSx	↓ to SCKx ↓ or SCKx ↑	120	—	—	ns	—
	TssL2scL		Input
SP51	TssH2doZ			↑ to SDOX Output	10	—	50	ns	See Note 4
SP51	TssH2doZ		SSx	↑ to SDOX Output	10	—	50	ns	See Note 4
			High-Impedance
SP52	TscH2ssH			↑ after SCKx Edge	1.5 TCY + 40	—	—	ns	—
SP52	TscH2ssH		SSx	↑ after SCKx Edge	1.5 TCY + 40	—	—	ns	—
	TscL2ssH
SP60	TssL2doV		SDOx Data Output Valid after		—	—	50	ns	—
			SSx Edge

Note 1: These parameters are characterized but not tested in manufacturing.

2:Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3:The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this specification.

4:Assumes 50 pF load on all SPIx pins.

DS70283B-page 264

Preliminary

♥ 2007 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

FIGURE 23-18: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)

SCLx
IM31	IM34
IM30	IM33

SDAx

Start	Stop
Condition	Condition

Note: Refer to Figure 23-1 for load conditions.

FIGURE 23-19: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)

IM20	IM11	IM21
SCLx	IM10
SCLx
IM11	IM26	IM33
IM10	IM25	IM33

SDAx

IM40	IM40	IM45

SDAx

Out

Note: Refer to Figure 23-1 for load conditions.

♥ 2007 Microchip Technology Inc.

Preliminary

DS70283B-page 265

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

TABLE 23-36: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)

				Standard Operating Conditions: 3.0V to 3.6V
AC CHARACTERISTICS				(unless otherwise stated)
AC CHARACTERISTICS				Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
				Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
					-40°C ≤ TA ≤ +125°C for Extended
Param	Symbol	Characteristic		Min(1)	Max	Units	Conditions
No.

IM10	TLO:SCL	Clock Low Time	100 kHz mode	TCY/2 (BRG + 1)	—	μs	—
			400 kHz mode	TCY/2 (BRG + 1)	—	μs	—
			1 MHz mode(2)	TCY/2 (BRG + 1)	—	μs	—
IM11	THI:SCL	Clock High Time	100 kHz mode	TCY/2 (BRG + 1)	—	μs	—
			400 kHz mode	TCY/2 (BRG + 1)	—	μs	—
			1 MHz mode(2)	TCY/2 (BRG + 1)	—	μs	—
IM20	TF:SCL	SDAx and SCLx	100 kHz mode	—	300	ns	CB is specified to be
		Fall Time					from 10 to 400 pF
		Fall Time	400 kHz mode	20 + 0.1 CB	300	ns	from 10 to 400 pF
			400 kHz mode	20 + 0.1 CB	300	ns
			1 MHz mode(2)	—	100	ns
IM21	TR:SCL	SDAx and SCLx	100 kHz mode	—	1000	ns	CB is specified to be
		Rise Time					from 10 to 400 pF
		Rise Time	400 kHz mode	20 + 0.1 CB	300	ns	from 10 to 400 pF
			400 kHz mode	20 + 0.1 CB	300	ns
			1 MHz mode(2)	—	300	ns
IM25	TSU:DAT	Data Input	100 kHz mode	250	—	ns	—
		Setup Time
		Setup Time	400 kHz mode	100	—	ns
			400 kHz mode	100	—	ns
			1 MHz mode(2)	40	—	ns
IM26	THD:DAT	Data Input	100 kHz mode	0	—	μs	—
		Hold Time
		Hold Time	400 kHz mode	0	0.9	μs
			400 kHz mode	0	0.9	μs
			1 MHz mode(2)	0.2	—	μs
IM30	TSU:STA	Start Condition	100 kHz mode	TCY/2 (BRG + 1)	—	μs	Only relevant for
		Setup Time					Repeated Start
		Setup Time	400 kHz mode	TCY/2 (BRG + 1)	—	μs	Repeated Start
			400 kHz mode	TCY/2 (BRG + 1)	—	μs	condition
			1 MHz mode(2)	TCY/2 (BRG + 1)	—	μs	condition
			1 MHz mode(2)	TCY/2 (BRG + 1)	—	μs
IM31	THD:STA	Start Condition	100 kHz mode	TCY/2 (BRG + 1)	—	μs	After this period the
		Hold Time					first clock pulse is
		Hold Time	400 kHz mode	TCY/2 (BRG + 1)	—	μs	first clock pulse is
			400 kHz mode	TCY/2 (BRG + 1)	—	μs	generated
			1 MHz mode(2)	TCY/2 (BRG + 1)	—	μs	generated
			1 MHz mode(2)	TCY/2 (BRG + 1)	—	μs
IM33	TSU:STO	Stop Condition	100 kHz mode	TCY/2 (BRG + 1)	—	μs	—
		Setup Time
		Setup Time	400 kHz mode	TCY/2 (BRG + 1)	—	μs
			400 kHz mode	TCY/2 (BRG + 1)	—	μs
			1 MHz mode(2)	TCY/2 (BRG + 1)	—	μs
IM34	THD:STO	Stop Condition	100 kHz mode	TCY/2 (BRG + 1)	—	ns	—
		Hold Time	400 kHz mode	TCY/2 (BRG + 1)	—	ns
			1 MHz mode(2)	TCY/2 (BRG + 1)	—	ns
IM40	TAA:SCL	Output Valid	100 kHz mode	—	3500	ns	—
		From Clock
		From Clock	400 kHz mode	—	1000	ns	—
			400 kHz mode	—	1000	ns	—
			1 MHz mode(2)	—	400	ns	—
IM45	TBF:SDA	Bus Free Time	100 kHz mode	4.7	—	μs	Time the bus must be
							free before a new
			400 kHz mode	1.3	—	μs	free before a new
			400 kHz mode	1.3	—	μs	transmission can start
			1 MHz mode(2)	0.5	—	μs	transmission can start
			1 MHz mode(2)	0.5	—	μs
IM50	CB	Bus Capacitive Loading		—	400	pF

Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit (I2C™)” in the “dsPIC33F Family Reference Manual”. Please see the Microchip web site for the latest dsPIC33F Family Reference Manual sections.

2:Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

DS70283B-page 266

Preliminary

♥ 2007 Microchip Technology Inc.

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

FIGURE 23-20: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)

SCLx
IS31	IS34
IS30	IS33

SDAx

Start	Stop
Condition	Condition

FIGURE 23-21: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

IS20

IS11

IS21

SCLx	IS10
SCLx
IS30	IS26	IS33
IS31	IS25	IS33

SDAx

IS40	IS40	IS45

SDAx

Out

♥ 2007 Microchip Technology Inc.

Preliminary

DS70283B-page 267

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

TABLE 23-37: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)

				Standard Operating Conditions: 3.0V to 3.6V
AC CHARACTERISTICS				(unless otherwise stated)
AC CHARACTERISTICS				Operating temperature		-40°C ≤ TA ≤ +85°C for Industrial
				Operating temperature		-40°C ≤ TA ≤ +85°C for Industrial
						-40°C ≤ TA ≤ +125°C for Extended
Param.	Symbol	Characteristic		Min	Max	Units	Conditions

IS10	TLO:SCL	Clock Low Time	100 kHz mode	4.7	—	μs	Device must operate at a
							minimum of 1.5 MHz
			400 kHz mode	1.3	—	μs	Device must operate at a
							minimum of 10 MHz
			1 MHz mode(1)	0.5	—	μs	—
IS11	THI:SCL	Clock High Time	100 kHz mode	4.0	—	μs	Device must operate at a
							minimum of 1.5 MHz
			400 kHz mode	0.6	—	μs	Device must operate at a
							minimum of 10 MHz
			1 MHz mode(1)	0.5	—	μs	—
IS20	TF:SCL	SDAx and SCLx	100 kHz mode	—	300	ns	CB is specified to be from
		Fall Time					10 to 400 pF
		Fall Time	400 kHz mode	20 + 0.1 CB	300	ns	10 to 400 pF
			400 kHz mode	20 + 0.1 CB	300	ns
			1 MHz mode(1)	—	100	ns
IS21	TR:SCL	SDAx and SCLx	100 kHz mode	—	1000	ns	CB is specified to be from
		Rise Time					10 to 400 pF
		Rise Time	400 kHz mode	20 + 0.1 CB	300	ns	10 to 400 pF
			400 kHz mode	20 + 0.1 CB	300	ns
			1 MHz mode(1)	—	300	ns
IS25	TSU:DAT	Data Input	100 kHz mode	250	—	ns	—
		Setup Time
		Setup Time	400 kHz mode	100	—	ns
			400 kHz mode	100	—	ns
			1 MHz mode(1)	100	—	ns
IS26	THD:DAT	Data Input	100 kHz mode	0	—	μs	—
		Hold Time
		Hold Time	400 kHz mode	0	0.9	μs
			400 kHz mode	0	0.9	μs
			1 MHz mode(1)	0	0.3	μs
IS30	TSU:STA	Start Condition	100 kHz mode	4.7	—	μs	Only relevant for Repeated
		Setup Time					Start condition
		Setup Time	400 kHz mode	0.6	—	μs	Start condition
			400 kHz mode	0.6	—	μs
			1 MHz mode(1)	0.25	—	μs
IS31	THD:STA	Start Condition	100 kHz mode	4.0	—	μs	After this period, the first
		Hold Time					clock pulse is generated
		Hold Time	400 kHz mode	0.6	—	μs	clock pulse is generated
			400 kHz mode	0.6	—	μs
			1 MHz mode(1)	0.25	—	μs
IS33	TSU:STO	Stop Condition	100 kHz mode	4.7	—	μs	—
		Setup Time
		Setup Time	400 kHz mode	0.6	—	μs
			400 kHz mode	0.6	—	μs
			1 MHz mode(1)	0.6	—	μs
IS34	THD:ST	Stop Condition	100 kHz mode	4000	—	ns	—
	O	Hold Time
	O	Hold Time	400 kHz mode	600	—	ns
			400 kHz mode	600	—	ns
			1 MHz mode(1)	250		ns
IS40	TAA:SCL	Output Valid	100 kHz mode	0	3500	ns	—
		From Clock
		From Clock	400 kHz mode	0	1000	ns
			400 kHz mode	0	1000	ns
			1 MHz mode(1)	0	350	ns
IS45	TBF:SDA	Bus Free Time	100 kHz mode	4.7	—	μs	Time the bus must be free
							before a new transmission
			400 kHz mode	1.3	—	μs	before a new transmission
			400 kHz mode	1.3	—	μs	can start
			1 MHz mode(1)	0.5	—	μs	can start
			1 MHz mode(1)	0.5	—	μs
IS50	CB	Bus Capacitive Loading		—	400	pF	—
Note 1:	Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

DS70283B-page 268

Preliminary

♥ 2007 Microchip Technology Inc.

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