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Signal

Direction

Description

reset

Input

The IP core asynchronously resets when you assert this

signal. You must deassert this signal synchronously to the

rising edge of the clock signal.

clock

Input

The main system clock. The IP core operates on the rising

edge of this signal.

control_av_address

Input

control slave port Avalon-MM address bus. Specifies a

word offset into the slave address space.

Note: Present only if you turn on Run-time control

of image size..

control_av_chipselect

Input

control slave port Avalon-MM chip select signal. When

you assert this signal, the control port ignores all other

signals unless you assert this signal.

Note: Present only if you turn on Run-time control

of image size..

control_av_readdata

Output

control slave port Avalon-MM read data bus. These

output lines are used for read transfers.

Note: Present only if you turn on Run-time control

of image size..

control_av_write

Input

control slave port Avalon-MM write signal. When you

assert this signal, the control port accepts new data from

the write data bus.

Note: Present only if you turn on Run-time control

of image size..

control_av_writedata

Input

control slave port Avalon-MM write data bus. These

input lines are used for write transfers.

Note: Present only if you turn on Run-time control

of image size..

dout_data

Output

dout port Avalon-ST data bus. This bus enables the

transfer of pixel data out of the IP core.

dout_endofpacket

Output

dout port Avalon-ST endofpacket signal. This signal

marks the end of an Avalon-ST packet.

dout_ready

Input

dout port Avalon-ST ready signal. The downstream

device asserts this signal when it is able to receive data.

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Signal

Direction

Description

dout_startofpacket

Output

dout port Avalon-ST startofpacket signal. This signal

marks the start of an Avalon-ST packet.

dout_valid

Output

dout port Avalon-ST valid signal. The IP core asserts this

signal when it produces data.

Table 19-5: Test Pattern Generator II Signals

Signal

Direction

Description

reset

Input

The IP core asynchronously resets when you assert this

signal. You must deassert this signal synchronously to the

rising edge of the clock signal.

clock

Input

The main system clock. The IP core operates on the rising

edge of this signal.

control_address

Input

control slave port Avalon-MM address bus. This bus

specifies a word offset into the slave address space.

control_write

Input

controlslave port Avalon-MM write signal. When you

assert this signal, the control port accepts new data from

the writedata bus.

control_writedata

Input

controlslave port Avalon-MM writedata bus. The IP

core uses these input lines for write transfers.

control_read

Output

control slave port Avalon-MM read signal. When you

assert this signal, the control port produces new data at

readdata.

control_readdata

Output

control slave port Avalon-MM readdatavalid bus. The

IP core uses these output lines for read transfers.

control_readdatavalid

Output

control slave port Avalon-MM readdata bus. The IP

core asserts this signal when the readdata bus contains

valid data in response to the read signal.

control_waitrequest

Output

control slave port Avalon-MM waitrequest signal.

control_byteenable

Output

control slave port Avalon-MM byteenable bus. This bus

enables specific byte lane or lanes during transfers.

Each bit in byteenable corresponds to a byte in

writedata and readdata.

• During writes, byteenable specifies which bytes are

being written to; the slave ignores other bytes.

• During reads, byteenable indicates which bytes the

master is reading. Slaves that simply return readdata

with no side effects are free to ignore byteenable

during reads.

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Test Pattern Generator Control Registers

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Signal

Direction

Description

dout_data

Output

dout port Avalon-ST data bus. This bus enables the

transfer of pixel data out of the IP core.

dout_endofpacket

Output

dout port Avalon-ST endofpacket signal. This signal

marks the end of an Avalon-ST packet.

dout_ready

Input

dout port Avalon-ST ready signal. The downstream

device asserts this signal when it is able to receive data.

dout_startofpacket

Output

dout port Avalon-ST startofpacket signal. This signal

marks the start of an Avalon-ST packet.

dout_valid

Output

dout port Avalon-ST valid signal. The IP core asserts this

signal when it produces data.

Address

Register

Description

0

Control

Bit 0 of this register is the Go bit, all other bits are unused.

Setting this bit to 0 causes the IP core to stop before control

information is read.

1

Status

Bit 0 of this register is the Status bit, all other bits are unused.

The IP core sets this address to 0 between frames. The IP core

sets this address to 1 while it is producing data and cannot be

stopped.

2

Output Width

The progressive height of the output frames or fields in pixels.

Note: Value from 32 up to the maximum specified in the

parameter editor.

3

Output Height

The width of the output frames or fields in pixels.

Note: Value from 32 up to the maximum specified in the

parameter editor.

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Address

Register

4

R/Y

The value of the R (or Y) color sample when the test pattern is

a uniform color background.

Note: Available only when the IP core is configured to

produce a uniform color background and run-time

control interface is enabled.

5

G/Cb

The value of the G (or Cb) color sample when the test pattern

6

B/Cr

The value of the B (or Cr) color sample when the test pattern

is a uniform color background.

Note: Available only when the IP core is configured to

produce a uniform color background and run-time

control interface is enabled.

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Test Pattern Generator Control Registers

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Address

Register

Description

4

Output Height

The width of the output frames or fields in pixels.

Note: Value from 32 up to the maximum specified in the

parameter editor.

5

R/Y

The value of the R (or Y) color sample when the test pattern is

a uniform color background.

Note: Available only when the IP core is configured to

produce a uniform color background and run-time

control interface is enabled.

6

G/Cb

The value of the G (or Cb) color sample when the test pattern

is a uniform color background.

Note: Available only when the IP core is configured to

produce a uniform color background and run-time

control interface is enabled.

7

B/Cr

The value of the B (or Cr) color sample when the test pattern

is a uniform color background.

Note: Available only when the IP core is configured to

produce a uniform color background and run-time

control interface is enabled.