Frame Buffer Signals

14-9

Signal

Directio

Description

n

clock

Input

The main system clock. The IP core operates on the

rising edge of this signal.

reset

Input

The IP core asynchronously resets when this signal is

high. You must deassert this signal synchronously to the

rising edge of the clock signal.

din_data

Input

din port Avalon-ST data bus. This bus enables the

transfer of pixel data into the IP core.

din_endofpacket

Input

din port Avalon-ST endofpacket signal. This signal

marks the end of an Avalon-ST packet.

din_ready

Output

din port Avalon-ST ready signal. This signal indicates

when the IP core is ready to receive data.

din_startofpacket

Input

din port Avalon-ST startofpacket signal. This signal

marks the start of an Avalon-ST packet.

din_valid

Input

din port Avalon-ST valid signal. This signal identifies

the cycles when the port must enter data.

dout_data

Output

dout port Avalon-ST data bus. This bus enables the

transfer of pixel data out of the IP core.

dout_endofpacket

Output

dout port Avalon-ST endofpacket signal. This signal

marks the end of an Avalon-ST packet.

dout_ready

Input

dout port Avalon-ST ready signal. The downstream

device asserts this signal when it is able to receive data.

dout_startofpacket

Output

dout port Avalon-ST startofpacket signal. This signal

marks the start of an Avalon-ST packet.

dout_valid

Output

dout port Avalon-ST valid signal. The IP core asserts

this signal when it produces data.

read_master_av_clock

Input

read_master port clock signal. The interface operates

on the rising edge of the clock signal.

14-10

Frame Buffer Signals

UG-VIPSUITE

2015.01.23

Signal

Directio

Description

n

read_master_av_reset

Input

read_master port reset signal. The interface asynchro

nously resets when this signal is high. You must deassert

this signal synchronously to the rising edge of the clock

signal.

read_master_av_address

Output

read_master port Avalon-MM address bus. This bus

specifies a byte address in the Avalon-MM address space.

read_master_av_burstcount

Output

read_master port Avalon-MM burstcount signal. This

signal specifies the number of transfers in each burst.

read_master_av_read

Output

read_master port Avalon-MM read signal. The IP core

asserts this signal to indicate read requests from the

master to the system interconnect fabric.

read_master_av_readdata

Input

read_master port Avalon-MM readdata bus. These

input lines carry data for read transfers.

read_master_av_readdatavalid

Input

read_master port Avalon-MM readdatavalid signal.

The system interconnect fabric asserts this signal when

the requested read data has arrived.

read_master_av_waitrequest

Input

read_master port Avalon-MM waitrequest signal. The

system interconnect fabric asserts this signal to cause the

master port to wait.

write_master_av_clock

Input

write_master port clocksignal. The interface operates

on the rising edge of the clock signal.

write_master_av_reset

Input

write_master port reset signal. The interface

asynchronously resets when this signal is high. You must

deassert this signal synchronously to the rising edge of

the clock signal.

write_master_av_address

Output

write_master port Avalon-MM address bus. This bus

specifies a byte address in the Avalon-MM address space.

write_master_av_burstcount

Output

write_master port Avalon-MM burstcount signal. This

signal specifies the number of transfers in each burst.

write_master_av_waitrequest

Input

write_master port Avalon-MM waitrequest signal.

The system interconnect fabric asserts this signal to cause

the master port to wait.

write_master_av_write

Output

write_master port Avalon-MM write signal. The IP

core asserts this signal to indicate write requests from the

master to the system interconnect fabric.

write_master_av_writedata

Output

write_master port Avalon-MM writedata bus. These

output lines carry data for write transfers.

Frame Buffer Signals

14-11

Signal

Directio

Description

n

reader_control_av_chipselect

Input

reader control slave port Avalon-MM chipselect

signal. The reader control port ignores all other

signals unless you assert this signal.

reader_control_av_readdata

Output

reader control slave port Avalon-MM readdata bus.

The IP core uses these output lines for read transfers.

reader_control_av_write

Input

reader control slave port Avalon-MM write signal.

When you assert this signal, the reader control port

accepts new data from the writedata bus.

reader_control_av_writedata

Input

reader controlslave port Avalon-MM writedata bus.

The IP core uses these input lines for write transfers.

Signal

Directio

Description

n

writer_control_av_chipselect

Input

writer_control slave port Avalon-MM chipselect

signal. The writer_control port ignores all other

signals unless you assert this signal.

writer_control_av_readdata

Output

writer_control slave port Avalon-MM readdata bus.

The IP core uses these output lines for read transfers.

writer_control_av_write

Input

writer_controlslave port Avalon-MM write signal.

When you assert this signal, the ker_writer_control

port accepts new data from the writedata bus.

writer_control_av_writedata

Input

writer_controlslave port Avalon-MM writedata bus.

The IP core uses these input lines for write transfers.

Table 14-7: Signals for Frame Buffer II IP Core

Signal

Directio

Description

n

main_clock

Input

The main system clock. The IP core operates on the

rising edge of this signal.

main_reset

Input

The IP core asynchronously resets when this signal is

high. You must deassert this signal synchronously to the

rising edge of the clock signal.

14-12

Frame Buffer Signals

UG-VIPSUITE

2015.01.23

Signal

Directio

Description

n

mem_clock

Input

mem_master port clocksignal. The interface operates on

the rising edge of the clock signal.

mem_reset

Input

mem_master port reset signal. The interface asynchro

nously resets when this signal is high. You must deassert

this signal synchronously to the rising edge of the clock

signal.

din_data

Input

din port Avalon-ST data bus. This bus enables the

transfer of pixel data into the IP core.

din_endofpacket

Input

din port Avalon-ST endofpacket signal. This signal

marks the end of an Avalon-ST packet.

din_ready

Output

din port Avalon-ST ready signal. This signal indicates

when the IP core is ready to receive data.

din_startofpacket

Input

din port Avalon-ST startofpacket signal. This signal

marks the start of an Avalon-ST packet.

din_valid

Input

din port Avalon-ST valid signal. This signal identifies

the cycles when the port must enter data.

dout_data

Output

dout port Avalon-ST data bus. This bus enables the

transfer of pixel data out of the IP core.

dout_endofpacket

Output

dout port Avalon-ST endofpacket signal. This signal

marks the end of an Avalon-ST packet.

dout_ready

Input

dout port Avalon-ST ready signal. The downstream

device asserts this signal when it is able to receive data.

dout_startofpacket

Output

dout port Avalon-ST startofpacket signal. This signal

marks the start of an Avalon-ST packet.

dout_valid

Output

dout port Avalon-ST valid signal. The IP core asserts

this signal when it produces data.

mem_master_rd_address

Output

mem_master_rd port Avalon-MM address bus. This bus

specifies a byte address in the Avalon-MM address space.

mem_master_rd_burstcount

Output

mem_master_rd port Avalon-MM burstcount signal.

This signal specifies the number of transfers in each

burst.

mem_master_rd_read

Output

mem_master_rd port Avalon-MM read signal. The IP

core asserts this signal to indicate read requests from the

master to the system interconnect fabric.

mem_master_rd_readdata

Input

mem_master_rd port Avalon-MM readdata bus. These

input lines carry data for read transfers.

Frame Buffer Signals

14-13