UG-VIPSUITE

Stall Behavior and Error Recovery

1-11

2015.01.23

IP Core

Configuration

ALM

RAM

DSP

Scaler II

• Symbols in parallel = 3

1,010

12

12

• Scaling algorithm = Polyphase

• Enable run-time control of input/output

frame size = On

• Vertical/horizontal filter taps = 4

• Vertical/horizontal filter phases = 14

Test Pattern

• Color space = RGB

65

0

0

Generator

• Run-time control of image size = Off

Trace System

• Buffer size = 8192

1,224

12

0

• Bit width of capture interface(s) = 32

• Number of inputs = 2

Video and Image Processing Suite Overview

Altera Corporation

1-12

Stall Behavior and Error Recovery

UG-VIPSUITE

2015.01.23

IP Core

Stall Behavior

Error Recovery

2D FIR Filter

• Has a delay of a little more than N–1

• Resolution is not configurable at

lines between data input and output

run time.

in the case of a N×N 2D FIR Filter.

• Does not read the control

• Delay caused by to line buffering

packets passed through it.

internal to the IP core.

An error condition occurs if an

endofpacket signal is received too

early or too late for the compile time

configured frame size. In either case,

the 2D FIR Filter always creates

output video packets of the

configured size.

• If an input video packet has a late

endofpacket signal, then the

extra data is discarded.

• If an input video packet has an

early endofpacket signal, then

the video frame is padded with

an undefined combination of the

last input pixels.

Altera Corporation

Video and Image Processing Suite Overview

1-14

Stall Behavior and Error Recovery

UG-VIPSUITE

2015.01.23

IP Core

Stall Behavior

Error Recovery

Chroma Resampler

All modes stall for a few cycles between

• Receiving an early endofpacket

frames and between lines.

signal—the IP core stalls its input

Latency from input to output varies

but continues writing data until

it has sent an entire frame.

depending on the operation mode of

• Not receiving an endofpacket

the IP core.

signal at the end of a frame—the

• The only modes with latency of

IP core discards date until it

more than a few cycles are 4:2:0 to

finds end-of-packet.

4:2:2 and 4:2:0 to 4:4:4—

corresponding to one line of 4:2:0

data

• The quantities of data input and

output are not equal because this is a

rate-changing function.

• Always produces the same number

of lines that it accept—but the

number of samples in each line

varies according to the subsampling

pattern used.

When not stalled, always processes one

sample from the more fully sampled

side on each clock cycle. For example,

the subsampled side pauses for one

third of the clock cycles in the 4:2:2 case

or half of the clock cycles in the 4:2:0

case.

Clipper/

• Stalls for a few cycles between lines

• Receiving an early endofpacket

Clipper II

and between frames.

signal—the IP core stalls its input

• Internal latency is less than 10

but continues writing data until

cycles.

it has sent an entire frame.

• During the processing of a line, it

• Not receiving an endofpacket

reads continuously but only writes

signal at the end of a frame—the

when inside the active picture area

IP core discards data until it

as defined by the clipping window

finds end-of-packet.

Clocked Video Input/

• Dictated by incoming video.

If an overflow is caused by a

Clocked Video Input II

• If its output FIFO is empty, during

downstream core failing to receive

horizontal and vertical blanking

data at the rate of the incoming

periods the IP core does not produce

video, the Clocked Video Input

any video data.

sends an early end of packet and

restart sending video data at the

start of the next frame or field.

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Video and Image Processing Suite Overview

UG-VIPSUITE

Stall Behavior and Error Recovery

1-15

2015.01.23

IP Core

Stall Behavior

Error Recovery

Clocked Video Output/

• Dictated by outgoing video.

• Receiving an early end of packet

Clocked Video Output II

• If its input FIFO is empty, during

— the IP core resynchronizes the

horizontal and vertical blanking

outgoing video data to the

periods the IP core stalls and does

incoming video data on the next

not take in any more video data.

start of packet it receives.

• Receiving a late end of packet—

the IP core resynchronizes the

outgoing video data to the

incoming video immediately.

• If Genlock functionality is

enabled—the IP core does not

resynchronize to the incoming

video.

Color Plane Sequencer

• Stalls for approximately 10 cycles

• Processes video packets per line

after processing each line of a video

until the IP core receives an

frame.

endofpacket signal on din0—

• Between frames the IP core stalls for

the line width is taken from the

approximately 30 cycles

control packets on din0.

• Receiving endofpacket signal on

either din0 or din1: IP core

ceases output.

For the number of cycles left to

finish the line, the IP core continues

to drain the inputs that have not

indicated end of packet.

• Drains din0 until it receives an

endofpacket signal on this port

(unless it has already indicated

end of packet), and stalls for up

to one line after this

endofpacket signal.

• Signals end of packet on its

outputs and continue to drain its

inputs that have not indicated

end of packet.

Video and Image Processing Suite Overview

Altera Corporation

1-16

Stall Behavior and Error Recovery

UG-VIPSUITE

2015.01.23

IP Core

Stall Behavior

Error Recovery

Color Space Converter/

• Only stalls between frames and not

• Processes video packets until the

Color Space Converter II

between rows.

IP core receives an endofpacket

• It has no internal buffering apart

signal; the control packets are

from the registers of its processing

not used.

pipeline—only a few clock cycles of

• Any mismatch of the

latency.

endofpacket signal and the

frame size is propagated

unchanged to the next IP core.

Control Synchronizer

• Stalls for several cycles between

• Processes video packets until the

packets.

IP core receives an endofpacket

• Stalls when it enters a triggered state

signal; the image width, height

while it writes to the Avalon-MM

and interlaced fields of the

Slave ports of other IP cores.

control data packets are not

• If the slaves do not provide a wait

compared against the following

request signal, the stall lasts for no

video data packet.

more than 50 clock cycles.

• Any mismatch of the

Otherwise the stall is of unknown

endofpacket signal and the

length.

frame size of video data packet is

propagated unchanged to the

next IP core.

Altera Corporation

Video and Image Processing Suite Overview

1-18

Stall Behavior and Error Recovery

UG-VIPSUITE

2015.01.23

IP Core

Stall Behavior

Error Recovery

Deinterlacer II/

Stores input video fields in the external

• Generates a line with the correct

Broadcast Deinterlacer

memory and concurrently uses these

length if the IP core receives an

input video fields to construct deinter

early endofpacket signal.

laced frames.

• The video data in the output

• Stalls up to 50 clock cycles for the

frame is valid up to the point

first output frame.

where the IP core receives the

• Additional delay of one line for

endofpacket signal.

second output frame because the IP

• The IP core then stops

core generates the last line of the

generating output until it

output frame before accepting the

receives the next startofpacket

first line of the next input field.

signal.

• Delay of two lines for the following

• Receiving a late endofpacket

output frames, which includes the

signal, the IP core completes

one line delay from the second

generating the current output

output frame.

frame with the correct number of

• For all subsequent fields, the delay

lines as indicated by the last

alternates between one and two

control packet.

lines.

• The IP core discards the

subsequent input lines. Once it

receives a startofpacket signal,

the IP core performs a soft reset

and it loses the stored cadence or

motion values.

• The IP core resumes deinter

lacing when it receives the next

startofpacket signal.

Frame Reader

Stalls the output for several tens of

The IP core can be stalled due to

cycles before producing each video data

backpressure, without consequences

packet, and stalls the output where

and it does not require error

there is contention for access to

recovery.

external memory.

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Video and Image Processing Suite Overview

UG-VIPSUITE

Stall Behavior and Error Recovery

1-19

2015.01.23

IP Core

Stall Behavior

Error Recovery

Frame Buffer/

• May stall frequently and read or

• Does not rely on the content of

Frame Buffer II

write less than once per clock cycle

the control packets to determine

during control packet processing.

the size of the image data

• During data processing at the input

packets.

or at the output, the stall behavior of

• Any early or late endofpacket

the IP core is largely decided by

signal and any mismatch

contention on the memory bus.

between the size of the image

data packet and the content of

the control packet is propagated

unchanged to the next IP core.

• Does not write outside the

memory allocated for each non-

image and image Avalon-ST

video packet; packets are

truncated if they are larger than

the maximum size defined at

compile time.

Gamma Corrector

• Stalls only between frames and not

• Processes video packets until the

between rows.

IP core receives an endofpacket

• Has no internal buffering aside from

signal; non-image packets are

the registers of its processing

propagated but the content of

pipeline— only a few clock cycles of

control packets is ignored.

latency

• Any mismatch of the

endofpacket signal and the

frame size is propagated

unchanged to the next IP core.

Interlacer

• Alternates between propagating and

• Receiving endofpacket signal

discarding a row from the input port

later than expected: discards

while producing an interlaced

extra data.

output field—the output port is

• Receiving an early endofpacket

inactive every other row.

signal: the current output field is

• The delay from input to output is a

interrupted as soon as possible

few clock cycles when pixels are

and may be padded with a single

propagated.

undefined pixel.

Video and Image Processing Suite Overview

Altera Corporation

UG-VIPSUITE

Stall Behavior and Error Recovery

1-21

2015.01.23

IP Core

Stall Behavior

Error Recovery

Scaler II

Enabling run-time control of

resolutions affects stalling between

frames:

• With no run-time control: about 10

cycles of delay before the stall

behavior begins, and about 20 cycles

of further stalling between each

output line.

• With run-time control of

resolutions: about additional 25

cycles of delay between frames.

Switch/

• Only stalls its inputs when

Switch II

performing an output switch.

• Before switching its outputs, the IP

—

core synchronizes all its inputs and

the inputs may be stalled during this

synchronization.

Test Pattern Generator/

• All modes stall for a few cycles after

Test Pattern Generator II

a field control packet, and between

lines.

• When producing a line of image

data, the IP core produces one

—

sample output on every clock cycle,

but it can be stalled without

consequences if other functions

down the data path are not ready

and exert backpressure.

Video and Image Processing Suite Overview

Altera Corporation