
- •Contents
- •1. Video and Image Processing Suite Overview
- •Release Information
- •Device Family Support
- •Latency
- •In-System Performance and Resource Guidance
- •Stall Behavior and Error Recovery
- •2. Interfaces
- •Video Formats
- •Avalon-ST Video Protocol
- •Video Data Packets
- •Static Parameters of Video Data Packets
- •Control Data Packets
- •Ancillary Data Packets
- •User-Defined and Altera-Reserved Packets
- •Packet Propagation
- •Transmission of Avalon-ST Video Over Avalon-ST Interfaces
- •Packet Transfer Examples
- •Avalon-MM Slave Interfaces
- •Specification of the Type of Avalon-MM Slave Interfaces
- •Avalon-MM Master Interfaces
- •Specification of the Type of Avalon-MM Master Interfaces
- •Buffering of Non-Image Data Packets in Memory
- •3. Getting Started
- •IP Catalog and Parameter Editor
- •Specifying IP Core Parameters and Options
- •Installing and Licensing IP Cores
- •OpenCore Plus IP Evaluation
- •4. Clocked Video Interface IP Cores
- •Control Port
- •Clocked Video Input Format Detection
- •Interrupts
- •Clocked Video Output Video Modes
- •Interrupts
- •Generator Lock
- •Underflow and Overflow
- •Timing Constraints
- •Handling Ancillary Packets
- •Modules for Clocked Video Input II IP Core
- •Clocked Video Interface Parameter Settings
- •Clocked Video Interface Signals
- •Clocked Video Interface Control Registers
- •5. 2D FIR Filter IP Core
- •Calculation Precision
- •Coefficient Precision
- •Result to Output Data Type Conversion
- •2D FIR IP Core Parameter Settings
- •2D FIR Filter Signals
- •2D FIR Filter Control Registers
- •6. Video Mixing IP Cores
- •Alpha Blending
- •Video Mixing Parameter Settings
- •Video Mixing Signals
- •Video Mixing Control Registers
- •7. Chroma Resampler IP Core
- •Horizontal Resampling (4:2:2)
- •Vertical Resampling (4:2:0)
- •Chroma Resampler Parameter Settings
- •Chroma Resampler Signals
- •8. Video Clipping IP Cores
- •Video Clipping Parameter Settings
- •Video Clipping Signals
- •Video Clipping Control Registers
- •9. Color Plane Sequencer IP Core
- •Combining Color Patterns
- •Rearranging Color Patterns
- •Splitting and Duplicating
- •Subsampled Data
- •Color Plane Sequencer Parameter Settings
- •Color Plane Sequencer Signals
- •10. Color Space Conversion IP Cores
- •Input and Output Data Types
- •Color Space Conversion
- •Result of Output Data Type Conversion
- •Color Space Conversion Parameter Settings
- •Color Space Conversion Signals
- •Color Space Conversion Control Registers
- •11. Control Synchronizer IP Core
- •Using the Control Synchronizer IP Core
- •Control Synchronizer Parameter Settings
- •Control Synchronizer Signals
- •Control Synchronizer Control Registers
- •12. Deinterlacing IP Cores
- •Deinterlacing Methods
- •Bob with Scanline Duplication
- •Bob with Scanline Interpolation
- •Weave
- •Motion-Adaptive
- •Sobel-Based HQ Mode
- •Pass-Through Mode for Progressive Frames
- •Frame Buffering
- •Frame Rate Conversion
- •Bandwidth Requirement Calculations for 10-bit YCbCr Video
- •Behavior When Unexpected Fields are Received
- •Handling of Avalon-ST Video Control Packets
- •Deinterlacing Parameter Settings
- •Deinterlacing Signals
- •Deinterlacing Control Registers
- •Design Guidelines for Broadcast Deinterlacer IP Core
- •13. Frame Reader IP Core
- •Single-Cycle Color Patterns
- •Frame Reader Output Pattern and Memory Organization
- •Frame Reader Parameter Settings
- •Frame Reader Signals
- •Frame Reader Control Registers
- •14. Frame Buffer IP Cores
- •Double Buffering
- •Triple Buffering
- •Locked Frame Rate Conversion
- •Handling of Avalon-ST Video Control Packets
- •Color Format
- •Frame Buffer Parameter Settings
- •Frame Buffer Signals
- •Frame Buffer Control Registers
- •15. Gamma Corrector IP Core
- •Gamma Corrector Parameter Settings
- •Gamma Corrector Signals
- •Gamma Corrector Control Registers
- •16. Interlacer IP Core
- •Interlacer Parameter Settings
- •Interlacer Signals
- •Interlacer Control Registers
- •17. Scaler II IP Core
- •Nearest Neighbor Algorithm
- •Bilinear Algorithm
- •Bilinear Algorithmic Description
- •Polyphase and Bicubic Algorithm
- •Double-Buffering
- •Polyphase Algorithmic Description
- •Choosing and Loading Coefficients
- •Edge-Adaptive Scaling Algorithm
- •Scaler II Parameter Settings
- •Scaler II Signals
- •Scaler II Control Registers
- •18. Video Switching IP Cores
- •Mixer Layer Switching
- •Video Switching Parameter Settings
- •Video Switching Signals
- •Video Switching Control Registers
- •19. Test Pattern Generator IP Cores
- •Test Pattern
- •Generation of Avalon-ST Video Control Packets and Run-Time Control
- •Test Pattern Generator Parameter Settings
- •Test Pattern Generator Signals
- •Test Pattern Generator Control Registers
- •20. Trace System IP Core
- •Trace System Parameter Settings
- •Trace System Signals
- •Operating the Trace System from System Console
- •Loading the Project and Connecting to the Hardware
- •Trace Within System Console
- •TCL Shell Commands
- •21. Avalon-ST Video Monitor IP Core
- •Packet Visualization
- •Monitor Settings
- •Avalon-ST Video Monitor Parameter Settings
- •Avalon-ST Video Monitor Signals
- •Avalon-ST Video Monitor Control Registers
- •Avalon-ST Video Class Library
- •Running the Tests
- •Video File Reader Test
- •Example Test Environment
- •Video Field Life Cycle
- •Constrained Random Test
- •Complete Class Reference
- •c_av_st_video_control
- •c_av_st_video_data
- •c_av_st_video_file_io
- •c_av_st_video_item
- •c_av_st_video_source_sink_base
- •c_av_st_video_sink_bfm_’SINK
- •c_av_st_video_source_bfm_’SOURCE
- •c_av_st_video_user_packet
- •c_pixel
- •Raw Video Data Format
- •Cadence Detection and Reverse Pulldown in the Deinterlacer II IP Core
- •Document Revision History
- •How to Contact Altera

UG-VIPSUITE |
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In-System Performance and Resource Guidance |
1-7 |
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2015.01.23 |
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IP Core |
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Mode |
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Latency |
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Method: Motion-adaptive |
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1 field + 2 lines |
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Frame buffering: None |
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• Output frame rate: As input |
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field rate |
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Method: Motion-adaptive, |
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1 field + 2 lines, or 2 lines |
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video-over-film mode |
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Broadcast Deinterlacer |
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• Frame buffering: 3 input |
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fields are buffered |
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• Output frame rate: As input |
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field rate |
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40% to 60% (depending on |
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phasing) of the time, the core |
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performs a weave forward so |
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there is no initial field of latency. |
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Frame Buffer/ Frame Buffer II |
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All modes |
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1 frame + O (lines) |
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Frame Reader |
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No latency issues. |
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Gamma Corrector |
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All modes |
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O (cycles) |
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Interlacer |
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All modes |
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O (cycles) |
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Scaler II |
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Scaling algorithm: Polyphase |
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(N–1) lines + O (cycles) |
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• Number of vertical taps: N |
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Switch/ Switch II |
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All modes |
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2 cycles |
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Test Pattern Generator/ |
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No latency issues. |
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Test Pattern Generator II |
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In-System Performance and Resource Guidance
The performance and resource data provided for your guidance.
Note: Run your own synthesis and fMAX trials to confirm the listed IP cores meet your system require ments.
Video and Image Processing Suite Overview |
Altera Corporation |
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Send Feedback

1-8 |
In-System Performance and Resource Guidance |
UG-VIPSUITE |
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2015.01.23 |
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Table 1-5: Performance and Resource Data Using Arria V Devices
The following data are obtained through a 4K test design example using an Arria V device (5AGXFB3H4F35C4). The general settings for the design is 8 bits per color plane; 2 pixels in parallel. The target fMAX is 148.5 MHz.
IP Core |
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Configuration |
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ALM |
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RAM |
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DSP |
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Mixer II |
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Number of color planes in parallel = 3 |
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1,591 |
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0 |
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0 |
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Inputs = 4 |
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Output = 1 |
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• Internal Test Pattern Generator |
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Clocked Video |
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Number of color planes in parallel = 3 |
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540 |
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26 |
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0 |
Input II |
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• Sync signals = On separate wires |
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• Pixel FIFO size = 4096 pixels |
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• Use control port = On |
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Clocked Video |
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Number of color planes in parallel = 3 |
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2,504 |
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49 |
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0 |
Output II |
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• Sync signals = On separate wires |
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• Pixel FIFO size = 4096 pixels |
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• Use control port = On |
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• Run-time configurable video modes = 4 |
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Color Space |
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Run-time control = On |
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1,515 |
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0 |
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18 |
Converter II |
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• Color model conversion = RGb to YCbCr |
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Broadcast Deinter |
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Number of color planes in parallel = 2 |
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11,516 |
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145 |
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34 |
lacer |
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• Avalon-MM master local ports width = |
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256 |
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• FIFO depths = 512 |
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• Run-time control = Off |
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Frame Buffer II |
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Number of color planes in parallel = 2 |
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1,472 |
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19 |
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0 |
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• Avalon-MM master ports width = 256 |
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• Read/write FIFO depth = 128 |
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• Frame dropping = On |
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• Frame repeating = On |
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Test Pattern |
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Color space = RGB |
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135 |
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0 |
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Generator II |
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• Run-time control of image size = On |
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Altera Corporation |
Video and Image Processing Suite Overview |
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Send Feedback

UG-VIPSUITE |
In-System Performance and Resource Guidance |
1-9 |
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2015.01.23 |
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Table 1-6: Performance and Resource Data Using Cyclone V Devices
The following data are obtained through a video design example using a Cyclone V device (5CGTFD9E5F35C7). The general setting for the design is 8 bits per color plane. The target fMAX is 100 MHz.
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ALM |
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RAM |
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DSP |
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2D FIR Filter |
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• Number of color planes in sequence = 3 |
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581 |
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3 |
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• Filter size = 3×3 |
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• Runtime control = On |
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• Integer bits = 4 |
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• Fractional bits = 3 |
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Avalon-ST Video |
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• Number of color planes in parallel = 3 |
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1,035 |
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10 |
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Monitor |
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• Capture video pixel data = On |
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Avalon-ST Video |
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• Number of color planes in parallel = 3 |
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479 |
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9 |
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0 |
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Monitor |
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• Capture video pixel data = Off |
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Alpha Blending |
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• Number of color planes in parallel = 3 |
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1,324 |
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1 |
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24 |
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Mixer |
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• Number of layers being mixed = 5 |
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• Alpha blending = On |
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Chroma |
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• 4:2:2, number of color planes in parallel |
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591 |
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0 |
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Resampler |
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(din) = 2 |
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• 4:4:4, number of color planes in parallel |
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(dout) = 3 |
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• Horizontal filtering algorithm = Filtered |
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• Luma adaptive = On |
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Clipper II |
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• Number of pixels (color planes) in parallel |
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402 |
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0 |
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= 3 |
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• Clipping method = Rectangle |
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• Enable runtime control of clipping |
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parameters = On |
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Clocked Video |
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• Number of color planes in parallel = 3 |
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257 |
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13 |
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0 |
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Input |
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• Sync signals = On separate wires |
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• Pixel FIFO size = 2048 pixels |
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• Use control port = On |
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Clocked Video |
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• Number of color planes in sequence = 2 |
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317 |
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9 |
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0 |
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Input |
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• Sync signals = Embedded |
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• Pixel FIFO size = 2048 pixels |
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• Use control port = On |
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Video and Image Processing Suite Overview |
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Altera Corporation |
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Send Feedback |
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1-10 |
In-System Performance and Resource Guidance |
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UG-VIPSUITE |
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2015.01.23 |
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IP Core |
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Configuration |
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ALM |
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RAM |
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DSP |
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Clocked Video |
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• Number of color planes in parallel = 3 |
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512 |
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Output |
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• Sync signals = On separate wires |
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• Pixel FIFO size = 1024 pixels |
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• Use control port = On |
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• Run-time configurable video modes = 1 |
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Color Plane |
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• din0: Color planes in parallel = 4 |
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104 |
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Sequencer |
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• dout0: Color planes in parallel = 3 |
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• dout1: Color planes in parallel = 1 |
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Color Space |
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• Color plane configuration = Three color |
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284 |
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planes in parallel |
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• Run-time control = Off |
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• Color model conversion = CbCrY': SDTV |
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to Computer B'G'R' |
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• Coefficients integer bits = 2 |
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• Summands integer bits = 9 |
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• Coefficient and summand fractional bits = |
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8 |
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Deinterlacer II |
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• Number of color planes in parallel = 3 |
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3,655 |
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67 |
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3 |
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• Deinterlace algorithm = Motion adaptive |
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• Cadence detection algorithm = 3:2 detector |
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• Avalon-MM master local ports width = |
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128 |
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• FIFO depths = 64 |
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Frame Buffer |
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• Number of color planes in parallel = 3 |
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1,084 |
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19 |
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0 |
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• Avalon-MM master ports width = 128 |
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• Read/write FIFO depth = 64 |
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• Frame dropping = On |
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• Frame repetition = On |
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Frame Reader |
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• Number of color planes in parallel = 4 |
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756 |
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6 |
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0 |
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• Avalon-MM master port width = 128 |
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• Read master FIFO depth = 64 |
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• Use separate clocks for the Avalon-MM |
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master interfaces = On |
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Gamma Corrector |
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Number of color planes in parallel = 3 |
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142 |
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3 |
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0 |
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Altera Corporation |
Video and Image Processing Suite Overview |
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