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Файл:dsd13-gos / dsd-14=pdk / gpdk_referenceManual.pdf
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- •Overview
- •What makes up a PDK?
- •Installation of the PDK
- •PDK Install Directory Structure/Contents
- •Creation of a Design Project
- •Techfile Methodology
- •Schematic Design
- •Library Device Setup
- •Resistors
- •Capacitors
- •MOSFETS
- •Bipolar Transistors
- •Inductor
- •Supported Devices
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTOR
- •BIPOLARS
- •DIODES
- •Views provided
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTOR
- •BIPOLARS
- •DIODES
- •CDF parameters
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTOR
- •BIPOLARS
- •DIODES
- •Component Label Defaults
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTORS
- •BIPOLARS
- •DIODES
- •Spectre Models
- •Techfile Layers
- •Virtuoso XL
- •SYMBOLIC CONTACTS
- •Dracula Support
- •Diva Decks
- •DIVA DRC
- •DIVA EXTRACT
- •DIVA LVS
- •DIVA LPE/PRE
- •Assura Decks
- •Assura DRC
- •Assura LVS
- •Assura RCX
- •DEVICE SPECIFICATIONS
- •Data Source Table
- •Model and Layout Source
- •MOS FORMAL PARAMETERS
- •RESISTOR FORMAL PARAMETERS
- •CAPACITOR FORMAL PARAMETERS
- •INDUCTOR FORMAL PARAMETERS
- •BIPOLAR FORMAL PARAMETERS
- •DIODES FORMAL PARAMETERS
- •DEVICE DATASHEETS
- •nmos – Nmos Transistor
- •nmos (backend)
- •nmos3 (backend)
- •pmos – Pmos Transistor
- •pmos (backend)
- •pmos3 – Pmos Transistor
- •pmos3 (backend)
- •nplusres – Nplus Resistor
- •nplusres (backend)
- •polyres – Poly Resistor
- •polyres (backend)
- •mimcap – Metal to Metal Capacitor
- •mimcap (backend)
- •nmoscap – Nmos Transistor Configured as Cap
- •nmoscap (backend)
- •inductor – Metal 3 Inductor
- •inductor (backend)
- •vpnp – Vertical Bipolar PNP
- •vpnp (backend)
- •npn – Bipolar npn
- •npn (backend)
- •pnp – Bipolar pnp
- •pnp (backend)
- •ndio – N type Diode
- •ndio (backend)
- •pdio – N type Diode
- •pdio (backend)
- •DESIGN RULES
- •Layout Guidelines
- •Density Rules
- •Interconnect Capacitance Table
- •Coupling Capacitance Table
- •Sheet Resistance Table
11 Views provided
11.1MOSFETS
•Four terminals (D, G, S, B)
•symbol, spectre, auLvs, auCdl, ivpcell, layout (Pcells)
11.2RESISTORS
•Three terminals (PLUS, MINUS, B) for diffused resistor
•Two terminals (PLUS, MINUS) for poly resistor
•symbol, spectre, auLvs, auCdl, ivpcell, layout (Pcells)
11.3CAPACITORS
•Two terminals (PLUS, MINUS) for mimcap
•Three terminals (TOP, BOT, B) for nmoscap
•symbol, spectre, auLvs, auCdl, ivpcell, layout (Pcells)
11.4INDUCTOR
•Two terminals (PLUS, MINUS)
•symbol, spectre, auLvs, auCdl, ivpcell, layout (Pcells)
11.5BIPOLARS
•Three terminals (C, B, E)
•symbol, spectre, auLvs, auCdl, ivpcell, layout (Fixed for vpnp, Pcells for npn/pnp)
11.6DIODES
•Two terminals (PLUS, MINUS)
•symbol, spectre, auLvs, auCdl, ivpcell, layout (Pcells)
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