
- •Overview
- •What makes up a PDK?
- •Installation of the PDK
- •PDK Install Directory Structure/Contents
- •Creation of a Design Project
- •Techfile Methodology
- •Schematic Design
- •Library Device Setup
- •Resistors
- •Capacitors
- •MOSFETS
- •Bipolar Transistors
- •Inductor
- •Supported Devices
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTOR
- •BIPOLARS
- •DIODES
- •Views provided
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTOR
- •BIPOLARS
- •DIODES
- •CDF parameters
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTOR
- •BIPOLARS
- •DIODES
- •Component Label Defaults
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTORS
- •BIPOLARS
- •DIODES
- •Spectre Models
- •Techfile Layers
- •Virtuoso XL
- •SYMBOLIC CONTACTS
- •Dracula Support
- •Diva Decks
- •DIVA DRC
- •DIVA EXTRACT
- •DIVA LVS
- •DIVA LPE/PRE
- •Assura Decks
- •Assura DRC
- •Assura LVS
- •Assura RCX
- •DEVICE SPECIFICATIONS
- •Data Source Table
- •Model and Layout Source
- •MOS FORMAL PARAMETERS
- •RESISTOR FORMAL PARAMETERS
- •CAPACITOR FORMAL PARAMETERS
- •INDUCTOR FORMAL PARAMETERS
- •BIPOLAR FORMAL PARAMETERS
- •DIODES FORMAL PARAMETERS
- •DEVICE DATASHEETS
- •nmos – Nmos Transistor
- •nmos (backend)
- •nmos3 (backend)
- •pmos – Pmos Transistor
- •pmos (backend)
- •pmos3 – Pmos Transistor
- •pmos3 (backend)
- •nplusres – Nplus Resistor
- •nplusres (backend)
- •polyres – Poly Resistor
- •polyres (backend)
- •mimcap – Metal to Metal Capacitor
- •mimcap (backend)
- •nmoscap – Nmos Transistor Configured as Cap
- •nmoscap (backend)
- •inductor – Metal 3 Inductor
- •inductor (backend)
- •vpnp – Vertical Bipolar PNP
- •vpnp (backend)
- •npn – Bipolar npn
- •npn (backend)
- •pnp – Bipolar pnp
- •pnp (backend)
- •ndio – N type Diode
- •ndio (backend)
- •pdio – N type Diode
- •pdio (backend)
- •DESIGN RULES
- •Layout Guidelines
- •Density Rules
- •Interconnect Capacitance Table
- •Coupling Capacitance Table
- •Sheet Resistance Table

21.13ndio – N type Diode
Spectre Netlist
Spectre Model Name = “dion”
D0 ( PLUS MINUS ) dion area=1e-12 m=1
DIVA LVS Netlist
DIVA Device Name = “ndio”
; ndio Instance /D0 = auLvs device D0 d ndio PLUS MINUS
i 0 ndio PLUS MINUS " area 1e-12 m 1.0 "
CDL Netlist
CDL Device Name = “DN”
DD0 PLUS MINUS DN 1e-12
Assura Netlist Assura auLvs Device Name = “ndio”
c ndio DIO POS B MINUS B ;;
*2 pins
*2 nets
*0 instances
i D0 ndio PLUS MINUS ; area 1e-12 m 1 ;

ndio (backend)
PLUS |
MINUS |
|
Area |
|
Device Layers |
Layer |
Color and Fill |
|
|
DIOdummy
Nimp / Oxide
Pimp / Oxide
Cont
Metal1
|
Device Derivation |
Device |
Layer Derivation |
Recognition |
DIOdummy AND Nimp |
PLUS |
DIOdummy AND Pimp |
MINUS |
DIOdummy AND Nimp |
|
LVS Comparison |
Parameter |
Calculation |
area |
Area of MINUS (illustrated above) |

21.14pdio – N type Diode
Spectre Netlist
Spectre Model Name = “diop”
D0 ( PLUS MINUS ) diop area=1e-12 m=1
DIVA LVS Netlist
DIVA Device Name = “pdio”
; pdio Instance /D0 = auLvs device D0 d pdio PLUS MINUS
i 0 pdio PLUS MINUS " area 1e-12 m 1.0 "
CDL Netlist
CDL Device Name = “DP”
DD0 PLUS MINUS DP 1e-12
Assura Netlist Assura auLvs Device Name = “pdio”
c pdio DIO POS B MINUS B ;;
*2 pins
*2 nets
*0 instances
i D0 pdio PLUS MINUS ; area 1e-12 m 1 ;

pdio (backend)
PLUS |
MINUS |
Area |
|
|
Device Layers |
Layer |
Color and Fill |
|
|
DIOdummy
Nwell
Nimp / Oxide
Pimp / Oxide
Cont
Metal1
|
Device Derivation |
Device |
Layer Derivation |
Recognition |
DIOdummy AND Pimp AND Nwell |
PLUS |
DIOdummy AND Pimp AND Nwell |
MINUS |
DIOdummy AND Nimp AND Nwell |
|
LVS Comparison |
Parameter |
Calculation |
area |
Area of PLUS (illustrated above) |