- •Overview
- •What makes up a PDK?
- •Installation of the PDK
- •PDK Install Directory Structure/Contents
- •Creation of a Design Project
- •Techfile Methodology
- •Schematic Design
- •Library Device Setup
- •Resistors
- •Capacitors
- •MOSFETS
- •Bipolar Transistors
- •Inductor
- •Supported Devices
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTOR
- •BIPOLARS
- •DIODES
- •Views provided
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTOR
- •BIPOLARS
- •DIODES
- •CDF parameters
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTOR
- •BIPOLARS
- •DIODES
- •Component Label Defaults
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTORS
- •BIPOLARS
- •DIODES
- •Spectre Models
- •Techfile Layers
- •Virtuoso XL
- •SYMBOLIC CONTACTS
- •Dracula Support
- •Diva Decks
- •DIVA DRC
- •DIVA EXTRACT
- •DIVA LVS
- •DIVA LPE/PRE
- •Assura Decks
- •Assura DRC
- •Assura LVS
- •Assura RCX
- •DEVICE SPECIFICATIONS
- •Data Source Table
- •Model and Layout Source
- •MOS FORMAL PARAMETERS
- •RESISTOR FORMAL PARAMETERS
- •CAPACITOR FORMAL PARAMETERS
- •INDUCTOR FORMAL PARAMETERS
- •BIPOLAR FORMAL PARAMETERS
- •DIODES FORMAL PARAMETERS
- •DEVICE DATASHEETS
- •nmos – Nmos Transistor
- •nmos (backend)
- •nmos3 (backend)
- •pmos – Pmos Transistor
- •pmos (backend)
- •pmos3 – Pmos Transistor
- •pmos3 (backend)
- •nplusres – Nplus Resistor
- •nplusres (backend)
- •polyres – Poly Resistor
- •polyres (backend)
- •mimcap – Metal to Metal Capacitor
- •mimcap (backend)
- •nmoscap – Nmos Transistor Configured as Cap
- •nmoscap (backend)
- •inductor – Metal 3 Inductor
- •inductor (backend)
- •vpnp – Vertical Bipolar PNP
- •vpnp (backend)
- •npn – Bipolar npn
- •npn (backend)
- •pnp – Bipolar pnp
- •pnp (backend)
- •ndio – N type Diode
- •ndio (backend)
- •pdio – N type Diode
- •pdio (backend)
- •DESIGN RULES
- •Layout Guidelines
- •Density Rules
- •Interconnect Capacitance Table
- •Coupling Capacitance Table
- •Sheet Resistance Table
21.5 nplusres – Nplus Resistor
Spectre Netlist
Spectre Model Name = “nplusres”
R1 (PLUS MINUS B) nplusres r=4.6K Area=6e-12 Perim=2.12e-05
DIVA LVS Netlist
DIVA Device Name = “nplusres”
; nplusres Instance /R1 = auLvs device R1
d nplusres PLUS MINUS B (p PLUS MINUS)
i 1 nplusres PLUS MINUS B " r 4.6e3 w 600e-9 "
CDL Netlist
CDL Device Name = “NR”
RR1 PLUS MINUS 4.6K $[NR]
Assura Netlist
Assura auLvs Device Name = “nplusres”
c nplusres RES IN B OUT B SUBSTRATE B ;;
*3 pins
*3 nets
*0 instances
i R1 nplusres PLUS MINUS ; r 4600 w 6e-07 ;
nplusres (backend)
Width |
Length |
|
|
Device Layers |
Layer |
Color and Fill |
|
|
Oxide
Nimp
Resdum (Marker Layer)
Cont
Metal1
|
Device Derivation |
Device |
Layer Derivation |
Recognition |
Oxide AND Nimp AND Resdum |
PLUS |
Oxide NOT Resdum |
MINUS |
Oxide NOT Resdum |
B |
Substrate |
|
LVS Comparison |
Parameter |
Calculation |
Length |
Contact to Contact (illustrated above) |
Width |
Oxide Width (illustrated above) |
Resistance |
sheet resistance * Length / Width |
* PLUS and MINUS are PERMUTABLE
21.6 polyres – Poly Resistor
Spectre Netlist
Spectre Model Name = “resistor”
R1 (PLUS MINUS) resistor r=115
DIVA LVS Netlist
DIVA Device Name = “polyres”
; polyres Instance /R1 = auLvs device R1 d polyres PLUS MINUS (p PLUS MINUS)
i 1 polyres PLUS MINUS " r 115 w 600e-9 "
CDL Netlist
CDL Device Name = “PR”
RR1 PLUS MINUS 115 $[PR]
Assura Netlist Assura auLvs Device Name = “polyres”
c polyres RES IN B OUT B ;;
*2 pins
*2 nets
*0 instances
i R1 polyres PLUS MINUS ; r 115 w 6e-07 ;
polyres (backend)
Width |
Length |
|
|
Device Layers |
Layer |
Color and Fill |
|
|
Poly
Resdum (Marker Layer)
Cont
Metal1
|
Device Derivation |
Device |
Layer Derivation |
Recognition |
Poly AND Resdum |
PLUS |
Poly NOT Resdum |
MINUS |
Poly NOT Resdum |
|
LVS Comparison |
Parameter |
Calculation |
Length |
Contact to Contact (illustrated above) |
Width |
Poly Width (illustrated above) |
Resistance |
sheet resistance * Length / Width |
* PLUS and MINUS are PERMUTABLE
