- •Overview
- •What makes up a PDK?
- •Installation of the PDK
- •PDK Install Directory Structure/Contents
- •Creation of a Design Project
- •Techfile Methodology
- •Schematic Design
- •Library Device Setup
- •Resistors
- •Capacitors
- •MOSFETS
- •Bipolar Transistors
- •Inductor
- •Supported Devices
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTOR
- •BIPOLARS
- •DIODES
- •Views provided
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTOR
- •BIPOLARS
- •DIODES
- •CDF parameters
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTOR
- •BIPOLARS
- •DIODES
- •Component Label Defaults
- •MOSFETS
- •RESISTORS
- •CAPACITORS
- •INDUCTORS
- •BIPOLARS
- •DIODES
- •Spectre Models
- •Techfile Layers
- •Virtuoso XL
- •SYMBOLIC CONTACTS
- •Dracula Support
- •Diva Decks
- •DIVA DRC
- •DIVA EXTRACT
- •DIVA LVS
- •DIVA LPE/PRE
- •Assura Decks
- •Assura DRC
- •Assura LVS
- •Assura RCX
- •DEVICE SPECIFICATIONS
- •Data Source Table
- •Model and Layout Source
- •MOS FORMAL PARAMETERS
- •RESISTOR FORMAL PARAMETERS
- •CAPACITOR FORMAL PARAMETERS
- •INDUCTOR FORMAL PARAMETERS
- •BIPOLAR FORMAL PARAMETERS
- •DIODES FORMAL PARAMETERS
- •DEVICE DATASHEETS
- •nmos – Nmos Transistor
- •nmos (backend)
- •nmos3 (backend)
- •pmos – Pmos Transistor
- •pmos (backend)
- •pmos3 – Pmos Transistor
- •pmos3 (backend)
- •nplusres – Nplus Resistor
- •nplusres (backend)
- •polyres – Poly Resistor
- •polyres (backend)
- •mimcap – Metal to Metal Capacitor
- •mimcap (backend)
- •nmoscap – Nmos Transistor Configured as Cap
- •nmoscap (backend)
- •inductor – Metal 3 Inductor
- •inductor (backend)
- •vpnp – Vertical Bipolar PNP
- •vpnp (backend)
- •npn – Bipolar npn
- •npn (backend)
- •pnp – Bipolar pnp
- •pnp (backend)
- •ndio – N type Diode
- •ndio (backend)
- •pdio – N type Diode
- •pdio (backend)
- •DESIGN RULES
- •Layout Guidelines
- •Density Rules
- •Interconnect Capacitance Table
- •Coupling Capacitance Table
- •Sheet Resistance Table
PDK
Reference Manual
GPDK
Process Design Kit
Revision 1.7
1 Overview
The purpose of this Reference Manual is to describe the technical details of the GPDK Generic Process Design Kit (“PDK”) provided by Cadence Design Systems, Inc. (“Cadence”). This PDK was tested for use with Cadence IC 4.4.6 and IC 5.0 Release.
This PDK requires the following environmental variables
“CDS_Netlisting_Mode” to be set to “Analog”
“CDSHOME” to be set to the Cadence DFII installation path
Cadence DFII Tool Training is not provided as part of this PDK.
THIS PDK IS INTENDED TO BE USED FOR DEMOSTRATION PURPOSES ONLY.
2 What makes up a PDK?
PDK stands for Process Design Kit. A PDK contains the process technology and needed information to do device-level design in the Cadence DFII environment.
PDK
Schematic
Symbols
& CDF
Analog
Simulation & callbacks
Spectre |
Foundry |
Models |
|
Fixed
Layouts
Parameterized
Cells
Techfile:
-Layer maps
-Layer props
-symbolics
-Connectivity
-VCR setup
Physical
Verification
-DRC
-LVS
-LPE
Cadence Tool
Schematic (Composer)
Simulation
Spectre
Analog Design Environment
Device Generation/Cell Design
Virtuoso XL (Advanced Layout Editor)
Interconnect Wire Editor/Routing
Virtuoso Custom Router (VCR)
Interactive Physical Verification
Diva, Dracula, Assura
Analog
Front-end
Design
VirtuosoXL
Layout
3 Installation of the PDK
Logon to the computer as the user who will own and maintain the PDK.
Choose a disk and directory under which the PDK will be installed. This disk should be exported to all client machines and must be mounted consistently across all client machines.
Connect to the directory where the PDK will be installed: cd <pdk_install_directory>
Extract the PDK from the archive using the following commands: zcat <path_to_pdk_tar_file>/pdk.tar.Z | tar xf -
The default permissions on the PDK have already been set to allow only the owner to have write, read and execute access. Other users will have only read and execute access.
4 PDK Install Directory Structure/Contents
REVISION - ASCII file containing the PDK revision history. cds.lib - file containing the Cadence initialization file. display.drf - ASCII version of display resources file icc.rules - Virtuoso Custom Router rules file
models - directory that will store the PDK models skill - directory containing the callback SKILL code
stream - directory containing the Cadence stream in and out maps techfile - ASCII version of technology file
gpdk - GPDK Process PDK Cadence Library
PDK_docs - directory containing the Cadence PDK documentation assura_gpdk_tech - directory containing the Assura verification files assura_tech.lib - file containing the Cadence Assura RCX initialization path
