dsd13-gos / dsd-14=pdk / Lect11_12
.pdf
Loading Callbacks
•You must make sure that the callbacks are loaded before you use the library.
•From the Command Interpreter Window type
load("path/callbacks.il")
•As an alternative, you can attach a callback file to a library. You attach callback files to a library by including a libInit.il file in that library. libInit.il is a text file that contains calls to load other SKILL files or contexts in the library or to initialize autoload properties. If you attach the file to the library, the file is automatically loaded whenever the library is opened. This guarantees that the functions are defined.
11 |
CADENCE CONFIDENTIAL |
Callback examples
|
procedure(gpdkCB() |
|
|
|
let((mult multVar) |
|
|
|
if( (mult = cdfParseFloatString(cdfgData->m->value)) && |
|
|
|
typep(mult) != 'flonum then |
|
|
|
multVar = t |
) |
|
|
if( mult == " " || mult == "" then |
|
|
|
artError("Multiplier value must be a positive integer - set to default" ) |
|
|
|
cdfgData->m->value = "1" |
|
|
|
mult = 1 |
|
|
|
multVar = nil |
) |
|
|
if(!multVar && (mult = fix(mult)) < 1 then |
|
|
|
artError("Multiplier value must be a positive integer - set to default" ) |
|
|
|
cdfgData->m->value = "1" |
|
|
|
mult = 1 |
|
|
|
multVar = nil |
) |
|
|
if(!multVar then |
|
|
|
cdfgData->m->value = sprintf(nil "%d" mult) ) )) |
|
|
|
|
|
|
|
|
|
|
12 |
CADENCE CONFIDENTIAL |
||
PDK Data Map
USER
CADENCE
Chip Designer
Schematic |
Simulation |
Layout |
Verification |
|
capture |
||||
|
|
|
PDK
Symbols |
Device |
Verification |
|
Layouts |
Rule Files |
||
|
CDF |
Techfile |
VXL Env |
Params SimInfo Callbacks
13 |
CADENCE CONFIDENTIAL |
PDK Device Layout
•Physical device layouts are required to produce correct by construction circuit design layouts.
•Typically three different methods to create PDK device layouts are used.
1.Create a custom device layout (hand-drawn) 2.Use fixed device layouts (pre-drawn)
3.Produce parameterized cells for each device (Pcells)
14 |
CADENCE CONFIDENTIAL |
PDK Device Layout (Hand-Drawn)
•Layout designer draws every layer for every device to produce the layout.
•Advantage – Can be used to create the most compact layout.
•Disadvantage – Layout development time is longer.
•Disadvantage – Probability of layouts errors is greater.
15 |
CADENCE CONFIDENTIAL |
PDK Device Layout (Pre-Drawn)
•Layout designer places pre-drawn fixed devices to produce the layout.
•Advantage – Best match with the spectre models used for
simulation.
• Disadvantage - Limits the configurations of device layouts available for use.
16 |
CADENCE CONFIDENTIAL |
PDK Device Layout (Pcell)
•Parameterized cells (Pcells) are developed as part of the PDK.
•Advantage – Greater flexibility in the configurations of device
layouts available for use.
• Advantage – Works best in the Virtuoso XL environment. Direct link between schematic and layout devices.
• Disadvantage – Pcell development expertise is required.
17 |
CADENCE CONFIDENTIAL |
What is a Parameterized Cell?
•A parameterized cell, or pcell, is a programmable design entity that lets you create a customized instance each time you place it. Pcells provide the following advantages:
•Speed up entering layout data by eliminating the need to create duplicate versions of the same functional part
•Save disk space by creating a library of cells for similar parts that are all linked to the same source
•Eliminate errors that can result in maintaining multiple versions of the same cell
•Eliminate the need to explode levels of hierarchy when you want to change a small detail of a design
18 |
CADENCE CONFIDENTIAL |
Creating a Pcell
There are two methods for creating pcells in the Design Framework II environment:
•Graphically, using the pcell editing commands in the Virtuoso layout editor
•Textually, using Cadence SKILL commands
19 |
CADENCE CONFIDENTIAL |
Advantages of SKILL Pcells
There are several advantages to creating pcells with SKILL:
•Easier creation of complex designs
•Easier maintenance of pcell code
•Process portability and independence
20 |
CADENCE CONFIDENTIAL |